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https://github.com/RPCS3/llvm-mirror.git
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300 lines
9.4 KiB
LLVM
300 lines
9.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse3 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512
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; Test ADDSUB ISel patterns.
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; Functions below are obtained from the following source:
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;
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; typedef double double2 __attribute__((ext_vector_type(2)));
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; typedef double double4 __attribute__((ext_vector_type(4)));
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; typedef float float4 __attribute__((ext_vector_type(4)));
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; typedef float float8 __attribute__((ext_vector_type(8)));
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;
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; float4 test1(float4 A, float4 B) {
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; float4 X = A - B;
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; float4 Y = A + B;
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; return (float4){X[0], Y[1], X[2], Y[3]};
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; }
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;
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; float8 test2(float8 A, float8 B) {
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; float8 X = A - B;
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; float8 Y = A + B;
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; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], Y[7]};
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; }
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;
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; double4 test3(double4 A, double4 B) {
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; double4 X = A - B;
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; double4 Y = A + B;
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; return (double4){X[0], Y[1], X[2], Y[3]};
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; }
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;
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; double2 test4(double2 A, double2 B) {
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; double2 X = A - B;
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; double2 Y = A + B;
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; return (double2){X[0], Y[1]};
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; }
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define <4 x float> @test1(<4 x float> %A, <4 x float> %B) {
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; SSE-LABEL: test1:
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; SSE: # BB#0:
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; SSE-NEXT: addsubps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test1:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%sub = fsub <4 x float> %A, %B
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%add = fadd <4 x float> %A, %B
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%vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %vecinit6
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}
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define <8 x float> @test2(<8 x float> %A, <8 x float> %B) {
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; SSE-LABEL: test2:
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; SSE: # BB#0:
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; SSE-NEXT: addsubps %xmm2, %xmm0
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; SSE-NEXT: addsubps %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test2:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%sub = fsub <8 x float> %A, %B
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%add = fadd <8 x float> %A, %B
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%vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x float> %vecinit14
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}
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define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
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; SSE-LABEL: test3:
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; SSE: # BB#0:
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; SSE-NEXT: addsubpd %xmm2, %xmm0
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; SSE-NEXT: addsubpd %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test3:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%sub = fsub <4 x double> %A, %B
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%add = fadd <4 x double> %A, %B
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%vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x double> %vecinit6
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}
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define <2 x double> @test4(<2 x double> %A, <2 x double> %B) #0 {
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; SSE-LABEL: test4:
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; SSE: # BB#0:
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; SSE-NEXT: addsubpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test4:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%add = fadd <2 x double> %A, %B
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%sub = fsub <2 x double> %A, %B
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%vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %vecinit2
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}
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define <16 x float> @test5(<16 x float> %A, <16 x float> %B) {
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; SSE-LABEL: test5:
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; SSE: # BB#0:
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; SSE-NEXT: addsubps %xmm4, %xmm0
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; SSE-NEXT: addsubps %xmm5, %xmm1
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; SSE-NEXT: addsubps %xmm6, %xmm2
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; SSE-NEXT: addsubps %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test5:
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; AVX1: # BB#0:
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; AVX1-NEXT: vaddsubps %ymm2, %ymm0, %ymm0
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; AVX1-NEXT: vaddsubps %ymm3, %ymm1, %ymm1
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: test5:
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; AVX512: # BB#0:
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; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm2
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; AVX512-NEXT: vsubps %zmm1, %zmm0, %zmm0
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; AVX512-NEXT: vmovdqa32 {{.*#+}} zmm1 = [0,17,2,19,4,21,6,23,8,25,10,27,12,29,14,31]
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; AVX512-NEXT: vpermt2ps %zmm2, %zmm1, %zmm0
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; AVX512-NEXT: retq
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%add = fadd <16 x float> %A, %B
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%sub = fsub <16 x float> %A, %B
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%vecinit2 = shufflevector <16 x float> %sub, <16 x float> %add, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
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ret <16 x float> %vecinit2
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}
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define <8 x double> @test6(<8 x double> %A, <8 x double> %B) {
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; SSE-LABEL: test6:
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; SSE: # BB#0:
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; SSE-NEXT: addsubpd %xmm4, %xmm0
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; SSE-NEXT: addsubpd %xmm5, %xmm1
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; SSE-NEXT: addsubpd %xmm6, %xmm2
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; SSE-NEXT: addsubpd %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test6:
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; AVX1: # BB#0:
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; AVX1-NEXT: vaddsubpd %ymm2, %ymm0, %ymm0
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; AVX1-NEXT: vaddsubpd %ymm3, %ymm1, %ymm1
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: test6:
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; AVX512: # BB#0:
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; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm2
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; AVX512-NEXT: vsubpd %zmm1, %zmm0, %zmm0
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; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm1 = [0,9,2,11,4,13,6,15]
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; AVX512-NEXT: vpermt2pd %zmm2, %zmm1, %zmm0
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; AVX512-NEXT: retq
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%add = fadd <8 x double> %A, %B
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%sub = fsub <8 x double> %A, %B
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%vecinit2 = shufflevector <8 x double> %sub, <8 x double> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x double> %vecinit2
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}
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define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
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; SSE-LABEL: test1b:
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; SSE: # BB#0:
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; SSE-NEXT: addsubps (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test1b:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubps (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %B
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%add = fadd <4 x float> %A, %1
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%sub = fsub <4 x float> %A, %1
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%vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %vecinit6
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}
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define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
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; SSE-LABEL: test2b:
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; SSE: # BB#0:
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; SSE-NEXT: addsubps (%rdi), %xmm0
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; SSE-NEXT: addsubps 16(%rdi), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test2b:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubps (%rdi), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = load <8 x float>, <8 x float>* %B
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%add = fadd <8 x float> %A, %1
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%sub = fsub <8 x float> %A, %1
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%vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x float> %vecinit14
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}
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define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
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; SSE-LABEL: test3b:
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; SSE: # BB#0:
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; SSE-NEXT: addsubpd (%rdi), %xmm0
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; SSE-NEXT: addsubpd 16(%rdi), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test3b:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = load <4 x double>, <4 x double>* %B
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%add = fadd <4 x double> %A, %1
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%sub = fsub <4 x double> %A, %1
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%vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x double> %vecinit6
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}
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define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
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; SSE-LABEL: test4b:
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; SSE: # BB#0:
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; SSE-NEXT: addsubpd (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test4b:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %B
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%sub = fsub <2 x double> %A, %1
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%add = fadd <2 x double> %A, %1
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%vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %vecinit2
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}
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define <4 x float> @test1c(<4 x float> %A, <4 x float>* %B) {
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; SSE-LABEL: test1c:
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; SSE: # BB#0:
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; SSE-NEXT: addsubps (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test1c:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubps (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %B
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%add = fadd <4 x float> %A, %1
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%sub = fsub <4 x float> %A, %1
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%vecinit6 = shufflevector <4 x float> %add, <4 x float> %sub, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
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ret <4 x float> %vecinit6
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}
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define <8 x float> @test2c(<8 x float> %A, <8 x float>* %B) {
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; SSE-LABEL: test2c:
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; SSE: # BB#0:
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; SSE-NEXT: addsubps (%rdi), %xmm0
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; SSE-NEXT: addsubps 16(%rdi), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test2c:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubps (%rdi), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = load <8 x float>, <8 x float>* %B
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%add = fadd <8 x float> %A, %1
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%sub = fsub <8 x float> %A, %1
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%vecinit14 = shufflevector <8 x float> %add, <8 x float> %sub, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
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ret <8 x float> %vecinit14
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}
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define <4 x double> @test3c(<4 x double> %A, <4 x double>* %B) {
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; SSE-LABEL: test3c:
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; SSE: # BB#0:
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; SSE-NEXT: addsubpd (%rdi), %xmm0
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; SSE-NEXT: addsubpd 16(%rdi), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test3c:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = load <4 x double>, <4 x double>* %B
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%add = fadd <4 x double> %A, %1
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%sub = fsub <4 x double> %A, %1
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%vecinit6 = shufflevector <4 x double> %add, <4 x double> %sub, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
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ret <4 x double> %vecinit6
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}
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define <2 x double> @test4c(<2 x double> %A, <2 x double>* %B) {
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; SSE-LABEL: test4c:
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; SSE: # BB#0:
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; SSE-NEXT: addsubpd (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test4c:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %B
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%sub = fsub <2 x double> %A, %1
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%add = fadd <2 x double> %A, %1
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%vecinit2 = shufflevector <2 x double> %add, <2 x double> %sub, <2 x i32> <i32 2, i32 1>
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ret <2 x double> %vecinit2
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}
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