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https://github.com/RPCS3/llvm-mirror.git
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d65007a4a3
llvm-svn: 79247
65 lines
2.0 KiB
C++
65 lines
2.0 KiB
C++
//===- SubtargetEmitter.h - Generate subtarget enumerations -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits subtarget enumerations.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SUBTARGET_EMITTER_H
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#define SUBTARGET_EMITTER_H
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#include "TableGenBackend.h"
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#include "llvm/Target/TargetInstrItineraries.h"
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#include <vector>
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#include <map>
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#include <string>
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namespace llvm {
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class SubtargetEmitter : public TableGenBackend {
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RecordKeeper &Records;
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std::string Target;
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bool HasItineraries;
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void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
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void FeatureKeyValues(raw_ostream &OS);
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void CPUKeyValues(raw_ostream &OS);
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unsigned CollectAllItinClasses(raw_ostream &OS,
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std::map<std::string, unsigned> &ItinClassesMap);
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void FormItineraryStageString(Record *ItinData, std::string &ItinString,
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unsigned &NStages);
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void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
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unsigned &NOperandCycles);
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void EmitStageAndOperandCycleData(raw_ostream &OS, unsigned NItinClasses,
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std::map<std::string, unsigned> &ItinClassesMap,
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std::vector<std::vector<InstrItinerary> > &ProcList);
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void EmitProcessorData(raw_ostream &OS,
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std::vector<std::vector<InstrItinerary> > &ProcList);
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void EmitProcessorLookup(raw_ostream &OS);
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void EmitData(raw_ostream &OS);
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void ParseFeaturesFunction(raw_ostream &OS);
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public:
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SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {}
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// run - Output the subtarget enumerations, returning true on failure.
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void run(raw_ostream &o);
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};
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} // End llvm namespace
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#endif
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