Silviu Baranga 5138c169b1 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. ...

llvm-svn: 156609

2012-05-11 09:28:27 +00:00

..

ARM

Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.

2012-05-11 09:10:54 +00:00

AsmParser

MC: Unknown assembler directives are now hard errors.

2012-05-01 18:38:27 +00:00

COFF

Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu

2012-03-25 09:02:19 +00:00

Disassembler

Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

2012-05-11 09:28:27 +00:00

ELF

Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu

2012-03-25 09:02:19 +00:00

MachO

Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits

2012-05-03 22:41:56 +00:00

MBlaze

Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu

2012-03-25 09:02:19 +00:00

Mips

This patch fixes 3 problems:

2012-04-16 18:20:26 +00:00

X86

Add retw and lretw instructions. Also, fix Intel syntax parsing for all

2012-04-11 01:10:53 +00:00