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649bad1e83
Additionally correct the Cortex-R7 definition to allow the FP16 feature. llvm-svn: 254900
19 lines
889 B
ArmAsm
19 lines
889 B
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-r7 -triple arm -show-encoding < %s 2>&1| \
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@ RUN: FileCheck %s --check-prefix=CHECK-FP16
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@ RUN: not llvm-mc -mcpu=cortex-r5 -triple arm -show-encoding < %s 2>&1 | \
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@ RUN: FileCheck %s --check-prefix=CHECK-NOFP16
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@ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee]
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@ CHECK-NOFP16: instruction requires: half-float conversions
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vcvtt.f32.f16 s7, s1
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@ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee]
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@ CHECK-NOFP16: instruction requires: half-float conversions
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vcvtt.f16.f32 s1, s7
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@ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee]
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@ CHECK-NOFP16: instruction requires: half-float conversions
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vcvtb.f32.f16 s7, s1
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@ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee]
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@ CHECK-NOFP16: instruction requires: half-float conversions
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vcvtb.f16.f32 s1, s7
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