Sander de Smalen 52edf6c6bd [AArch64][SVE] Asm: Support for insert element (INSR) instructions. ...

Insert general purpose register into shifted vector, e.g.
  insr    z0.s, w0
  insr    z0.d, x0

Insert SIMD&FP scalar register into shifted vector, e.g.
  insr    z0.b, b0
  insr    z0.h, h0
  insr    z0.s, s0
  insr    z0.d, d0

llvm-svn: 336979

2018-07-13 08:51:57 +00:00

..

AArch64

[AArch64][SVE] Asm: Support for insert element (INSR) instructions.

2018-07-13 08:51:57 +00:00

AMDGPU

[AMDGPU] Fix lit failures introduced in r335281

2018-06-21 22:30:09 +00:00

ARM

[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction

2018-07-06 08:03:12 +00:00

AsmParser

[X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104

2018-07-02 14:13:27 +00:00

AVR

[AVR] Implement some missing code paths

2017-12-11 11:01:27 +00:00

BPF

bpf: New disassembler testcases for 32-bit subregister support

2018-02-23 23:49:35 +00:00

COFF

[CodeView] Add prefix to CodeView registers.

2018-05-29 14:35:34 +00:00

Disassembler

Follow up of r336913: forgot to add the new test files.

2018-07-12 14:59:02 +00:00

ELF

Quick fix for some Windows bots

2018-07-11 18:51:15 +00:00

Hexagon

[Hexagon] Fix the value of HexagonII::TypeCVI_FIRST

2018-06-19 18:09:54 +00:00

Lanai

[lanai] Add more tests for assembly of conditional ALU ops

2016-07-11 17:58:16 +00:00

MachO

[MC] Error on a .zerofill directive in a non-virtual section

2018-07-02 17:29:43 +00:00

Mips

[mips] Addition of the [d]rem and [d]remu instructions

2018-07-09 13:06:44 +00:00

PowerPC

[PowerPC] Fix incorrectly encoded wait instruction

2018-06-25 19:28:27 +00:00

RISCV

[RISCV] Tail calls don't need to save return address

2018-06-21 14:37:09 +00:00

Sparc

[Sparc] Add support for 13-bit PIC

2018-06-11 05:50:08 +00:00

SystemZ

[SystemZ, AsmParser] Enable the mnemonic spell corrector.

2017-07-18 09:17:00 +00:00

WebAssembly

[WebAssembly] Ignore explicit section names for functions

2018-06-14 18:48:19 +00:00

X86

[X86][AsmParser] Don't consider %eip as a valid register outside of 32-bit mode.

2018-07-03 17:40:51 +00:00