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History

Oscar Fuentes ee36d9ce83 CMake: Add lib/Target/IA64/IA64Subtarget.cpp llvm-svn: 62394		2009-01-17 01:50:32 +00:00
..
CMakeLists.txt	CMake: Add lib/Target/IA64/IA64Subtarget.cpp	2009-01-17 01:50:32 +00:00
IA64.h	Tidy up #includes, deleting a bunch of unnecessary #includes.	2009-01-05 17:59:02 +00:00
IA64.td	Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.	2008-11-24 07:34:46 +00:00
IA64AsmPrinter.cpp	Add the private linkage.	2009-01-15 20:18:42 +00:00
IA64Bundling.cpp	Switch the MachineOperand accessors back to the short names like	2008-10-03 15:45:36 +00:00
IA64InstrBuilder.h
IA64InstrFormats.td
IA64InstrInfo.cpp	Tidy up #includes, deleting a bunch of unnecessary #includes.	2009-01-05 17:59:02 +00:00
IA64InstrInfo.h
IA64InstrInfo.td	Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.	2008-12-03 18:15:48 +00:00
IA64ISelDAGToDAG.cpp	Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph	2009-01-15 19:20:50 +00:00
IA64ISelLowering.cpp	Fix PR3274: when promoting the condition of a BRCOND node,	2009-01-01 15:52:00 +00:00
IA64ISelLowering.h	Fix PR3274: when promoting the condition of a BRCOND node,	2009-01-01 15:52:00 +00:00
IA64MachineFunctionInfo.h
IA64RegisterInfo.cpp	Switch the MachineOperand accessors back to the short names like	2008-10-03 15:45:36 +00:00
IA64RegisterInfo.h
IA64RegisterInfo.td
IA64Subtarget.cpp	Give IA64 a TargetSubtarget subclass, so that it can	2009-01-16 22:49:36 +00:00
IA64Subtarget.h	Give IA64 a TargetSubtarget subclass, so that it can	2009-01-16 22:49:36 +00:00
IA64TargetAsmInfo.cpp
IA64TargetAsmInfo.h
IA64TargetMachine.cpp	mark some targets as experimental. Andrew, if you think that Alpha is	2008-10-16 06:16:50 +00:00
IA64TargetMachine.h	Give IA64 a TargetSubtarget subclass, so that it can	2009-01-16 22:49:36 +00:00
Makefile	Removed trailing whitespace from Makefiles.	2009-01-09 16:44:42 +00:00
README

README

TODO:
  - Un-bitrot ISel
  - Hook up If-Conversion a la ARM target
  - Hook up all branch analysis functions
  - Instruction scheduling
  - Bundling
  - Dynamic Optimization
  - Testing and bugfixing
  - stop passing FP args in both FP *and* integer regs when not required
  - allocate low (nonstacked) registers more aggressively
  - clean up and thoroughly test the isel patterns.
  - fix stacked register allocation order: (for readability) we don't want
    the out? registers being the first ones used
  - fix up floating point
    (nb http://gcc.gnu.org/wiki?pagename=ia64%20floating%20point )
  - bundling!
    (we will avoid the mess that is:
     http://gcc.gnu.org/ml/gcc/2003-12/msg00832.html )
  - instruction scheduling (hmmmm! ;)
  - counted loop support
  - make integer + FP mul/div more clever (we have fixed pseudocode atm)
  - track and use comparison complements

INFO:
  - we are strictly LP64 here, no support for ILP32 on HP-UX. Linux users
    don't need to worry about this.
  - i have instruction scheduling/bundling pseudocode, that really works
    (has been tested, albeit at the perl-script level).
    so, before you go write your own, send me an email!

KNOWN DEFECTS AT THE CURRENT TIME:
  - C++ vtables contain naked function pointers, not function descriptors,
  which is bad. see http://llvm.cs.uiuc.edu/bugs/show_bug.cgi?id=406
  - varargs are broken
  - alloca doesn't work (indeed, stack frame layout is bogus)
  - no support for big-endian environments
  - (not really the backend, but...) the CFE has some issues on IA64.
    these will probably be fixed soon.
  
ACKNOWLEDGEMENTS:
  - Chris Lattner (x100)
  - Other LLVM developers ("hey, that looks familiar")

CONTACT:
  - You can email me at duraid@octopus.com.au. If you find a small bug,
    just email me. If you find a big bug, please file a bug report
    in bugzilla! http://llvm.cs.uiuc.edu is your one stop shop for all
    things LLVM.