Tim Northover 5802bd3e8d DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap
We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N),
const), but this is only valid if the bits above 16 on the source pattern are
0, the checks we were doing on this were slightly wrong before.

llvm-svn: 189348
2013-08-27 13:46:45 +00:00
..
2013-08-23 11:53:55 +00:00
2013-08-13 22:23:05 +00:00
2013-08-27 04:43:03 +00:00
2013-06-17 15:47:20 +00:00