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54 lines
1.9 KiB
LLVM
54 lines
1.9 KiB
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep cbd %t1.s | count 3 &&
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; RUN: grep chd %t1.s | count 3 &&
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; RUN: grep cwd %t1.s | count 6 &&
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; RUN: grep il %t1.s | count 4 &&
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; RUN: grep ilh %t1.s | count 3 &&
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; RUN: grep iohl %t1.s | count 1 &&
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; RUN: grep ilhu %t1.s | count 1 &&
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; RUN: grep shufb %t1.s | count 12 &&
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; RUN: grep 17219 %t1.s | count 1 &&
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; RUN: grep 22598 %t1.s | count 1 &&
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; RUN: grep -- -39 %t1.s | count 1 &&
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; RUN: grep 24 %t1.s | count 1 &&
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; RUN: grep 1159 %t1.s | count 1
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; ModuleID = 'vecinsert.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
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target triple = "spu-unknown-elf"
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; 67 -> 0x43, as 8-bit vector constant load = 0x4343 (17219)0x4343
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define <16 x i8> @test_v16i8(<16 x i8> %P, i8 %x) {
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entry:
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%tmp1 = insertelement <16 x i8> %P, i8 %x, i32 10
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%tmp1.1 = insertelement <16 x i8> %tmp1, i8 67, i32 7
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%tmp1.2 = insertelement <16 x i8> %tmp1.1, i8 %x, i32 15
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ret <16 x i8> %tmp1.2
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}
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; 22598 -> 0x5846
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define <8 x i16> @test_v8i16(<8 x i16> %P, i16 %x) {
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entry:
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%tmp1 = insertelement <8 x i16> %P, i16 %x, i32 5
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%tmp1.1 = insertelement <8 x i16> %tmp1, i16 22598, i32 7
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%tmp1.2 = insertelement <8 x i16> %tmp1.1, i16 %x, i32 2
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ret <8 x i16> %tmp1.2
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}
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; 1574023 -> 0x180487 (ILHU 24/IOHL 1159)
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define <4 x i32> @test_v4i32_1(<4 x i32> %P, i32 %x) {
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entry:
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%tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
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%tmp1.1 = insertelement <4 x i32> %tmp1, i32 1574023, i32 1
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%tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
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ret <4 x i32> %tmp1.2
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}
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; Should generate IL for the load
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define <4 x i32> @test_v4i32_2(<4 x i32> %P, i32 %x) {
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entry:
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%tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
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%tmp1.1 = insertelement <4 x i32> %tmp1, i32 -39, i32 1
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%tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
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ret <4 x i32> %tmp1.2
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}
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