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This patch adds basic CSKY branch instructions and symbol address series instructions. Those two kinds of instruction have relationship between each other, and it involves much work about Fixups. For now, basic instructions are enabled except for disassembler support. We would support to generate basic codegen asm firstly and delay disassembler work later. Differential Revision: https://reviews.llvm.org/D95029
170 lines
6.0 KiB
C++
170 lines
6.0 KiB
C++
//===-- CSKYAsmBackend.cpp - CSKY Assembler Backend -----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "CSKYAsmBackend.h"
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#include "MCTargetDesc/CSKYMCTargetDesc.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/MC/MCAsmLayout.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "csky-asmbackend"
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using namespace llvm;
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std::unique_ptr<MCObjectTargetWriter>
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CSKYAsmBackend::createObjectTargetWriter() const {
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return createCSKYELFObjectWriter();
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}
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const MCFixupKindInfo &
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CSKYAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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static llvm::DenseMap<unsigned, MCFixupKindInfo> Infos = {
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{CSKY::Fixups::fixup_csky_addr32, {"fixup_csky_addr32", 0, 32, 0}},
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{CSKY::Fixups::fixup_csky_pcrel_imm16_scale2,
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{"fixup_csky_pcrel_imm16_scale2", 0, 32, MCFixupKindInfo::FKF_IsPCRel}},
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{CSKY::Fixups::fixup_csky_pcrel_uimm16_scale4,
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{"fixup_csky_pcrel_uimm16_scale4", 0, 32, MCFixupKindInfo::FKF_IsPCRel}},
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{CSKY::Fixups::fixup_csky_pcrel_imm26_scale2,
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{"fixup_csky_pcrel_imm26_scale2", 0, 32, MCFixupKindInfo::FKF_IsPCRel}},
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{CSKY::Fixups::fixup_csky_pcrel_imm18_scale2,
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{"fixup_csky_pcrel_imm18_scale2", 0, 32, MCFixupKindInfo::FKF_IsPCRel}}};
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assert(Infos.size() == CSKY::NumTargetFixupKinds &&
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"Not all fixup kinds added to Infos array");
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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if (FirstTargetFixupKind <= Kind && Kind < FirstLiteralRelocationKind)
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return Infos[Kind];
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else if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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else
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return MCAsmBackend::getFixupKindInfo(FK_NONE);
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}
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static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext &Ctx) {
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switch (Fixup.getTargetKind()) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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return Value;
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case CSKY::fixup_csky_addr32:
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return Value & 0xffffffff;
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case CSKY::fixup_csky_pcrel_imm16_scale2:
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if (!isIntN(17, Value))
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Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");
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if (Value & 0x1)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned.");
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return (Value >> 1) & 0xffff;
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case CSKY::fixup_csky_pcrel_uimm16_scale4:
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if (!isUIntN(18, Value))
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Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");
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if (Value & 0x3)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned.");
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return (Value >> 2) & 0xffff;
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case CSKY::fixup_csky_pcrel_imm26_scale2:
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if (!isIntN(27, Value))
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Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");
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if (Value & 0x1)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned.");
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return (Value >> 1) & 0x3ffffff;
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case CSKY::fixup_csky_pcrel_imm18_scale2:
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if (!isIntN(19, Value))
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Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");
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if (Value & 0x1)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned.");
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return (Value >> 1) & 0x3ffff;
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}
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}
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void CSKYAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target,
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MutableArrayRef<char> Data, uint64_t Value,
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bool IsResolved,
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const MCSubtargetInfo *STI) const {
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MCFixupKind Kind = Fixup.getKind();
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if (Kind >= FirstLiteralRelocationKind)
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return;
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MCContext &Ctx = Asm.getContext();
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MCFixupKindInfo Info = getFixupKindInfo(Kind);
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if (!Value)
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return; // Doesn't change encoding.
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// Apply any target-specific value adjustments.
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Value = adjustFixupValue(Fixup, Value, Ctx);
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned Offset = Fixup.getOffset();
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unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
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assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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bool IsLittleEndian = (Endian == support::little);
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if (IsLittleEndian && (NumBytes == 4)) {
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Data[Offset + 0] |= uint8_t((Value >> 16) & 0xff);
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Data[Offset + 1] |= uint8_t((Value >> 24) & 0xff);
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Data[Offset + 2] |= uint8_t(Value & 0xff);
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Data[Offset + 3] |= uint8_t((Value >> 8) & 0xff);
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} else {
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for (unsigned I = 0; I != NumBytes; I++) {
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unsigned Idx = IsLittleEndian ? I : (NumBytes - 1 - I);
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Data[Offset + Idx] |= uint8_t((Value >> (I * 8)) & 0xff);
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}
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}
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}
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bool CSKYAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const {
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return false;
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}
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void CSKYAsmBackend::relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const {
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llvm_unreachable("CSKYAsmBackend::relaxInstruction() unimplemented");
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}
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bool CSKYAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
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if (Count % 2)
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return false;
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// MOV32 r0, r0
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while (Count >= 4) {
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OS.write("\xc4\x00\x48\x20", 4);
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Count -= 4;
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}
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// MOV16 r0, r0
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if (Count)
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OS.write("\x6c\x03", 2);
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return true;
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}
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MCAsmBackend *llvm::createCSKYAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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return new CSKYAsmBackend(STI, Options);
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}
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