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https://github.com/RPCS3/llvm-mirror.git
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f050da095d
Adjust sanity check in register parsing function to allow register name with more than 2 characters (e.g. ccr). Differential Revision: https://reviews.llvm.org/D101733
862 lines
23 KiB
C++
862 lines
23 KiB
C++
//===---- M68kAsmParser.cpp - Parse M68k assembly to MCInst instructions --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "M68kInstrInfo.h"
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#include "M68kRegisterInfo.h"
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#include "TargetInfo/M68kTargetInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCParser/MCTargetAsmParser.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/TargetRegistry.h"
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#include <sstream>
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#define DEBUG_TYPE "m68k-asm-parser"
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using namespace llvm;
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static cl::opt<bool> RegisterPrefixOptional(
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"m68k-register-prefix-optional", cl::Hidden,
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cl::desc("Enable specifying registers without the % prefix"),
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cl::init(false));
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namespace {
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/// Parses M68k assembly from a stream.
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class M68kAsmParser : public MCTargetAsmParser {
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const MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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const MCRegisterInfo *MRI;
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#define GET_ASSEMBLER_HEADER
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#include "M68kGenAsmMatcher.inc"
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// Helpers for Match&Emit.
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bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands,
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const uint64_t &ErrorInfo);
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bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
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bool emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const;
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bool parseRegisterName(unsigned int &RegNo, SMLoc Loc,
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StringRef RegisterName);
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OperandMatchResultTy parseRegister(unsigned int &RegNo);
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// Parser functions.
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void eatComma();
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bool isExpr();
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OperandMatchResultTy parseImm(OperandVector &Operands);
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OperandMatchResultTy parseMemOp(OperandVector &Operands);
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public:
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M68kAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
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const MCInstrInfo &MII, const MCTargetOptions &Options)
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: MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
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MCAsmParserExtension::Initialize(Parser);
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MRI = getContext().getRegisterInfo();
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
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unsigned Kind) override;
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
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OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
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SMLoc &EndLoc) override;
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bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc, OperandVector &Operands) override;
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bool ParseDirective(AsmToken DirectiveID) override;
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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uint64_t &ErrorInfo,
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bool MatchingInlineAsm) override;
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};
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struct M68kMemOp {
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enum class Kind {
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Addr,
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Reg,
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RegIndirect,
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RegPostIncrement,
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RegPreDecrement,
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RegIndirectDisplacement,
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RegIndirectDisplacementIndex,
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};
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// These variables are used for the following forms:
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// Addr: (OuterDisp)
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// Reg: %OuterReg
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// RegIndirect: (%OuterReg)
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// RegPostIncrement: (%OuterReg)+
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// RegPreDecrement: -(%OuterReg)
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// RegIndirectDisplacement: OuterDisp(%OuterReg)
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// RegIndirectDisplacementIndex:
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// OuterDisp(%OuterReg, %InnerReg.Size * Scale, InnerDisp)
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Kind Op;
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unsigned OuterReg;
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unsigned InnerReg;
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const MCExpr *OuterDisp;
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const MCExpr *InnerDisp;
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uint8_t Size : 4;
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uint8_t Scale : 4;
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const MCExpr *Expr;
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M68kMemOp() {}
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M68kMemOp(Kind Op) : Op(Op) {}
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void print(raw_ostream &OS) const;
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};
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/// An parsed M68k assembly operand.
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class M68kOperand : public MCParsedAsmOperand {
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typedef MCParsedAsmOperand Base;
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enum class Kind {
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Invalid,
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Token,
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Imm,
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MemOp,
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};
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Kind Kind;
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SMLoc Start, End;
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union {
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StringRef Token;
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int64_t Imm;
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const MCExpr *Expr;
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M68kMemOp MemOp;
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};
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public:
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M68kOperand(enum Kind Kind, SMLoc Start, SMLoc End)
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: Base(), Kind(Kind), Start(Start), End(End) {}
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SMLoc getStartLoc() const override { return Start; }
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SMLoc getEndLoc() const override { return End; }
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void print(raw_ostream &OS) const override;
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bool isMem() const override { return false; }
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bool isMemOp() const { return Kind == Kind::MemOp; }
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static void addExpr(MCInst &Inst, const MCExpr *Expr);
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// Reg
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bool isReg() const override;
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unsigned getReg() const override;
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void addRegOperands(MCInst &Inst, unsigned N) const;
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static std::unique_ptr<M68kOperand> createMemOp(M68kMemOp MemOp, SMLoc Start,
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SMLoc End);
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// Token
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bool isToken() const override;
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StringRef getToken() const;
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static std::unique_ptr<M68kOperand> createToken(StringRef Token, SMLoc Start,
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SMLoc End);
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// Imm
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bool isImm() const override;
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void addImmOperands(MCInst &Inst, unsigned N) const;
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static std::unique_ptr<M68kOperand> createImm(const MCExpr *Expr, SMLoc Start,
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SMLoc End);
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// Addr
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bool isAddr() const;
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void addAddrOperands(MCInst &Inst, unsigned N) const;
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// ARI
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bool isARI() const;
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void addARIOperands(MCInst &Inst, unsigned N) const;
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// ARID
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bool isARID() const;
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void addARIDOperands(MCInst &Inst, unsigned N) const;
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// ARII
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bool isARII() const;
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void addARIIOperands(MCInst &Inst, unsigned N) const;
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// ARIPD
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bool isARIPD() const;
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void addARIPDOperands(MCInst &Inst, unsigned N) const;
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// ARIPI
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bool isARIPI() const;
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void addARIPIOperands(MCInst &Inst, unsigned N) const;
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// PCD
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bool isPCD() const;
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void addPCDOperands(MCInst &Inst, unsigned N) const;
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// PCI
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bool isPCI() const;
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void addPCIOperands(MCInst &Inst, unsigned N) const;
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};
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} // end anonymous namespace.
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kAsmParser() {
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RegisterMCAsmParser<M68kAsmParser> X(getTheM68kTarget());
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}
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#define GET_MATCHER_IMPLEMENTATION
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#include "M68kGenAsmMatcher.inc"
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void M68kMemOp::print(raw_ostream &OS) const {
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switch (Op) {
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case Kind::Addr:
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OS << OuterDisp;
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break;
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case Kind::Reg:
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OS << '%' << OuterReg;
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break;
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case Kind::RegIndirect:
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OS << "(%" << OuterReg << ')';
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break;
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case Kind::RegPostIncrement:
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OS << "(%" << OuterReg << ")+";
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break;
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case Kind::RegPreDecrement:
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OS << "-(%" << OuterReg << ")";
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break;
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case Kind::RegIndirectDisplacement:
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OS << OuterDisp << "(%" << OuterReg << ")";
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break;
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case Kind::RegIndirectDisplacementIndex:
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OS << OuterDisp << "(%" << OuterReg << ", " << InnerReg << "." << Size
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<< ", " << InnerDisp << ")";
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break;
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}
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}
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void M68kOperand::addExpr(MCInst &Inst, const MCExpr *Expr) {
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if (auto Const = dyn_cast<MCConstantExpr>(Expr)) {
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Inst.addOperand(MCOperand::createImm(Const->getValue()));
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return;
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}
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Inst.addOperand(MCOperand::createExpr(Expr));
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}
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// Reg
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bool M68kOperand::isReg() const {
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return Kind == Kind::MemOp && MemOp.Op == M68kMemOp::Kind::Reg;
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}
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unsigned M68kOperand::getReg() const {
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assert(isReg());
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return MemOp.OuterReg;
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}
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void M68kOperand::addRegOperands(MCInst &Inst, unsigned N) const {
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assert(isReg() && "wrong operand kind");
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assert((N == 1) && "can only handle one register operand");
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Inst.addOperand(MCOperand::createReg(getReg()));
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}
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std::unique_ptr<M68kOperand> M68kOperand::createMemOp(M68kMemOp MemOp,
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SMLoc Start, SMLoc End) {
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auto Op = std::make_unique<M68kOperand>(Kind::MemOp, Start, End);
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Op->MemOp = MemOp;
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return Op;
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}
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// Token
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bool M68kOperand::isToken() const { return Kind == Kind::Token; }
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StringRef M68kOperand::getToken() const {
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assert(isToken());
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return Token;
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}
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std::unique_ptr<M68kOperand> M68kOperand::createToken(StringRef Token,
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SMLoc Start, SMLoc End) {
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auto Op = std::make_unique<M68kOperand>(Kind::Token, Start, End);
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Op->Token = Token;
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return Op;
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}
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// Imm
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bool M68kOperand::isImm() const { return Kind == Kind::Imm; }
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void M68kOperand::addImmOperands(MCInst &Inst, unsigned N) const {
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assert(isImm() && "wrong oeprand kind");
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assert((N == 1) && "can only handle one register operand");
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M68kOperand::addExpr(Inst, Expr);
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}
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std::unique_ptr<M68kOperand> M68kOperand::createImm(const MCExpr *Expr,
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SMLoc Start, SMLoc End) {
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auto Op = std::make_unique<M68kOperand>(Kind::Imm, Start, End);
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Op->Expr = Expr;
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return Op;
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}
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// Addr
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bool M68kOperand::isAddr() const {
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return isMemOp() && MemOp.Op == M68kMemOp::Kind::Addr;
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}
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void M68kOperand::addAddrOperands(MCInst &Inst, unsigned N) const {
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M68kOperand::addExpr(Inst, MemOp.OuterDisp);
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}
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// ARI
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bool M68kOperand::isARI() const {
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return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirect &&
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M68k::AR32RegClass.contains(MemOp.OuterReg);
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}
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void M68kOperand::addARIOperands(MCInst &Inst, unsigned N) const {
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Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
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}
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// ARID
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bool M68kOperand::isARID() const {
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return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacement &&
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M68k::AR32RegClass.contains(MemOp.OuterReg);
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}
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void M68kOperand::addARIDOperands(MCInst &Inst, unsigned N) const {
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M68kOperand::addExpr(Inst, MemOp.OuterDisp);
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Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
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}
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// ARII
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bool M68kOperand::isARII() const {
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return isMemOp() &&
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MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacementIndex &&
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M68k::AR32RegClass.contains(MemOp.OuterReg);
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}
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void M68kOperand::addARIIOperands(MCInst &Inst, unsigned N) const {
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M68kOperand::addExpr(Inst, MemOp.OuterDisp);
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Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
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Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
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}
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// ARIPD
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bool M68kOperand::isARIPD() const {
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return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegPreDecrement &&
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M68k::AR32RegClass.contains(MemOp.OuterReg);
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}
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void M68kOperand::addARIPDOperands(MCInst &Inst, unsigned N) const {
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Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
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}
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// ARIPI
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bool M68kOperand::isARIPI() const {
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return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegPostIncrement &&
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M68k::AR32RegClass.contains(MemOp.OuterReg);
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}
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void M68kOperand::addARIPIOperands(MCInst &Inst, unsigned N) const {
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Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
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}
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// PCD
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bool M68kOperand::isPCD() const {
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return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacement &&
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MemOp.OuterReg == M68k::PC;
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}
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void M68kOperand::addPCDOperands(MCInst &Inst, unsigned N) const {
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M68kOperand::addExpr(Inst, MemOp.OuterDisp);
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}
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// PCI
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bool M68kOperand::isPCI() const {
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return isMemOp() &&
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MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacementIndex &&
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MemOp.OuterReg == M68k::PC;
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}
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void M68kOperand::addPCIOperands(MCInst &Inst, unsigned N) const {
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M68kOperand::addExpr(Inst, MemOp.OuterDisp);
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Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
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}
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static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
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bool SP) {
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switch (RegNo) {
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case M68k::A0:
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case M68k::A1:
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case M68k::A2:
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case M68k::A3:
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case M68k::A4:
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case M68k::A5:
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case M68k::A6:
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return Address;
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case M68k::SP:
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return SP;
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case M68k::D0:
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case M68k::D1:
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case M68k::D2:
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case M68k::D3:
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case M68k::D4:
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case M68k::D5:
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case M68k::D6:
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case M68k::D7:
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return Data;
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case M68k::SR:
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case M68k::CCR:
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return false;
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default:
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llvm_unreachable("unexpected register type");
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return false;
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}
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}
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unsigned M68kAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
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unsigned Kind) {
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M68kOperand &Operand = (M68kOperand &)Op;
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switch (Kind) {
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case MCK_XR16:
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case MCK_SPILL:
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if (Operand.isReg() &&
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checkRegisterClass(Operand.getReg(), true, true, true)) {
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return Match_Success;
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}
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break;
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case MCK_AR16:
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case MCK_AR32:
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if (Operand.isReg() &&
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checkRegisterClass(Operand.getReg(), false, true, true)) {
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return Match_Success;
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}
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break;
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case MCK_AR32_NOSP:
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if (Operand.isReg() &&
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checkRegisterClass(Operand.getReg(), false, true, false)) {
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return Match_Success;
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}
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break;
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case MCK_DR8:
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case MCK_DR16:
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case MCK_DR32:
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if (Operand.isReg() &&
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checkRegisterClass(Operand.getReg(), true, false, false)) {
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return Match_Success;
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}
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break;
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case MCK_AR16_TC:
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if (Operand.isReg() &&
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((Operand.getReg() == M68k::A0) || (Operand.getReg() == M68k::A1))) {
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return Match_Success;
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}
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break;
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case MCK_DR16_TC:
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if (Operand.isReg() &&
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((Operand.getReg() == M68k::D0) || (Operand.getReg() == M68k::D1))) {
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return Match_Success;
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}
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break;
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case MCK_XR16_TC:
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if (Operand.isReg() &&
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((Operand.getReg() == M68k::D0) || (Operand.getReg() == M68k::D1) ||
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(Operand.getReg() == M68k::A0) || (Operand.getReg() == M68k::A1))) {
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return Match_Success;
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}
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break;
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}
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return Match_InvalidOperand;
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}
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bool M68kAsmParser::parseRegisterName(unsigned &RegNo, SMLoc Loc,
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StringRef RegisterName) {
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auto RegisterNameLower = RegisterName.lower();
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// CCR register
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if (RegisterNameLower == "ccr") {
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RegNo = M68k::CCR;
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return true;
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}
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// Parse simple general-purpose registers.
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if (RegisterNameLower.size() == 2) {
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static unsigned RegistersByIndex[] = {
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M68k::D0, M68k::D1, M68k::D2, M68k::D3, M68k::D4, M68k::D5,
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M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
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M68k::A4, M68k::A5, M68k::A6, M68k::SP,
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};
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switch (RegisterNameLower[0]) {
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case 'd':
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case 'a': {
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if (isdigit(RegisterNameLower[1])) {
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unsigned IndexOffset = (RegisterNameLower[0] == 'a') ? 8 : 0;
|
|
unsigned RegIndex = (unsigned)(RegisterNameLower[1] - '0');
|
|
if (RegIndex < 8) {
|
|
RegNo = RegistersByIndex[IndexOffset + RegIndex];
|
|
return true;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 's':
|
|
if (RegisterNameLower[1] == 'p') {
|
|
RegNo = M68k::SP;
|
|
return true;
|
|
} else if (RegisterNameLower[1] == 'r') {
|
|
RegNo = M68k::SR;
|
|
return true;
|
|
}
|
|
break;
|
|
|
|
case 'p':
|
|
if (RegisterNameLower[1] == 'c') {
|
|
RegNo = M68k::PC;
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
OperandMatchResultTy M68kAsmParser::parseRegister(unsigned &RegNo) {
|
|
bool HasPercent = false;
|
|
AsmToken PercentToken;
|
|
|
|
LLVM_DEBUG(dbgs() << "parseRegister "; getTok().dump(dbgs()); dbgs() << "\n");
|
|
|
|
if (getTok().is(AsmToken::Percent)) {
|
|
HasPercent = true;
|
|
PercentToken = Lex();
|
|
} else if (!RegisterPrefixOptional.getValue()) {
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
|
|
if (!Parser.getTok().is(AsmToken::Identifier)) {
|
|
if (HasPercent) {
|
|
getLexer().UnLex(PercentToken);
|
|
}
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
|
|
auto RegisterName = Parser.getTok().getString();
|
|
if (!parseRegisterName(RegNo, Parser.getLexer().getLoc(), RegisterName)) {
|
|
if (HasPercent) {
|
|
getLexer().UnLex(PercentToken);
|
|
}
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
|
|
Parser.Lex();
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
bool M68kAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
|
|
SMLoc &EndLoc) {
|
|
auto Result = tryParseRegister(RegNo, StartLoc, EndLoc);
|
|
if (Result != MatchOperand_Success) {
|
|
return Error(StartLoc, "expected register");
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
OperandMatchResultTy M68kAsmParser::tryParseRegister(unsigned &RegNo,
|
|
SMLoc &StartLoc,
|
|
SMLoc &EndLoc) {
|
|
StartLoc = getLexer().getLoc();
|
|
auto Result = parseRegister(RegNo);
|
|
EndLoc = getLexer().getLoc();
|
|
return Result;
|
|
}
|
|
|
|
bool M68kAsmParser::isExpr() {
|
|
switch (Parser.getTok().getKind()) {
|
|
case AsmToken::Identifier:
|
|
case AsmToken::Integer:
|
|
return true;
|
|
case AsmToken::Minus:
|
|
return getLexer().peekTok().getKind() == AsmToken::Integer;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
OperandMatchResultTy M68kAsmParser::parseImm(OperandVector &Operands) {
|
|
if (getLexer().isNot(AsmToken::Hash)) {
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
SMLoc Start = getLexer().getLoc();
|
|
Parser.Lex();
|
|
|
|
SMLoc End;
|
|
const MCExpr *Expr;
|
|
|
|
if (getParser().parseExpression(Expr, End)) {
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
Operands.push_back(M68kOperand::createImm(Expr, Start, End));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
OperandMatchResultTy M68kAsmParser::parseMemOp(OperandVector &Operands) {
|
|
SMLoc Start = getLexer().getLoc();
|
|
bool IsPD = false;
|
|
M68kMemOp MemOp;
|
|
|
|
// Check for a plain register.
|
|
auto Result = parseRegister(MemOp.OuterReg);
|
|
if (Result == MatchOperand_Success) {
|
|
MemOp.Op = M68kMemOp::Kind::Reg;
|
|
Operands.push_back(
|
|
M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
if (Result == MatchOperand_ParseFail) {
|
|
return Result;
|
|
}
|
|
|
|
// Check for pre-decrement & outer displacement.
|
|
bool HasDisplacement = false;
|
|
if (getLexer().is(AsmToken::Minus)) {
|
|
IsPD = true;
|
|
Parser.Lex();
|
|
} else if (isExpr()) {
|
|
if (Parser.parseExpression(MemOp.OuterDisp)) {
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
HasDisplacement = true;
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::LParen)) {
|
|
if (HasDisplacement) {
|
|
MemOp.Op = M68kMemOp::Kind::Addr;
|
|
Operands.push_back(
|
|
M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
|
|
return MatchOperand_Success;
|
|
} else if (IsPD) {
|
|
Error(getLexer().getLoc(), "expected (");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
return MatchOperand_NoMatch;
|
|
}
|
|
Parser.Lex();
|
|
|
|
// Check for constant dereference & MIT-style displacement
|
|
if (!HasDisplacement && isExpr()) {
|
|
if (Parser.parseExpression(MemOp.OuterDisp)) {
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
HasDisplacement = true;
|
|
|
|
// If we're not followed by a comma, we're a constant dereference.
|
|
if (getLexer().isNot(AsmToken::Comma)) {
|
|
MemOp.Op = M68kMemOp::Kind::Addr;
|
|
Operands.push_back(
|
|
M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
Parser.Lex();
|
|
}
|
|
|
|
Result = parseRegister(MemOp.OuterReg);
|
|
if (Result == MatchOperand_ParseFail) {
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
if (Result != MatchOperand_Success) {
|
|
Error(getLexer().getLoc(), "expected register");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
// Check for Index.
|
|
bool HasIndex = false;
|
|
if (Parser.getTok().is(AsmToken::Comma)) {
|
|
Parser.Lex();
|
|
|
|
Result = parseRegister(MemOp.InnerReg);
|
|
if (Result == MatchOperand_ParseFail) {
|
|
return Result;
|
|
}
|
|
|
|
if (Result == MatchOperand_NoMatch) {
|
|
Error(getLexer().getLoc(), "expected register");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
// TODO: parse size, scale and inner displacement.
|
|
MemOp.Size = 4;
|
|
MemOp.Scale = 1;
|
|
MemOp.InnerDisp = MCConstantExpr::create(0, Parser.getContext(), true, 4);
|
|
HasIndex = true;
|
|
}
|
|
|
|
if (Parser.getTok().isNot(AsmToken::RParen)) {
|
|
Error(getLexer().getLoc(), "expected )");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
Parser.Lex();
|
|
|
|
bool IsPI = false;
|
|
if (!IsPD && Parser.getTok().is(AsmToken::Plus)) {
|
|
Parser.Lex();
|
|
IsPI = true;
|
|
}
|
|
|
|
SMLoc End = getLexer().getLoc();
|
|
|
|
unsigned OpCount = IsPD + IsPI + (HasIndex || HasDisplacement);
|
|
if (OpCount > 1) {
|
|
Error(Start, "only one of post-increment, pre-decrement or displacement "
|
|
"can be used");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
if (IsPD) {
|
|
MemOp.Op = M68kMemOp::Kind::RegPreDecrement;
|
|
} else if (IsPI) {
|
|
MemOp.Op = M68kMemOp::Kind::RegPostIncrement;
|
|
} else if (HasIndex) {
|
|
MemOp.Op = M68kMemOp::Kind::RegIndirectDisplacementIndex;
|
|
} else if (HasDisplacement) {
|
|
MemOp.Op = M68kMemOp::Kind::RegIndirectDisplacement;
|
|
} else {
|
|
MemOp.Op = M68kMemOp::Kind::RegIndirect;
|
|
}
|
|
|
|
Operands.push_back(M68kOperand::createMemOp(MemOp, Start, End));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
void M68kAsmParser::eatComma() {
|
|
if (Parser.getTok().is(AsmToken::Comma)) {
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
bool M68kAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
|
|
SMLoc NameLoc, OperandVector &Operands) {
|
|
SMLoc Start = getLexer().getLoc();
|
|
Operands.push_back(M68kOperand::createToken(Name, Start, Start));
|
|
|
|
bool First = true;
|
|
while (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
|
|
if (!First) {
|
|
eatComma();
|
|
} else {
|
|
First = false;
|
|
}
|
|
|
|
auto MatchResult = MatchOperandParserImpl(Operands, Name);
|
|
if (MatchResult == MatchOperand_Success) {
|
|
continue;
|
|
}
|
|
|
|
// Add custom operand formats here...
|
|
SMLoc Loc = getLexer().getLoc();
|
|
Parser.eatToEndOfStatement();
|
|
return Error(Loc, "unexpected token parsing operands");
|
|
}
|
|
|
|
// Eat EndOfStatement.
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
bool M68kAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
|
|
|
|
bool M68kAsmParser::invalidOperand(SMLoc const &Loc,
|
|
OperandVector const &Operands,
|
|
uint64_t const &ErrorInfo) {
|
|
SMLoc ErrorLoc = Loc;
|
|
char const *Diag = 0;
|
|
|
|
if (ErrorInfo != ~0U) {
|
|
if (ErrorInfo >= Operands.size()) {
|
|
Diag = "too few operands for instruction.";
|
|
} else {
|
|
auto const &Op = (M68kOperand const &)*Operands[ErrorInfo];
|
|
if (Op.getStartLoc() != SMLoc()) {
|
|
ErrorLoc = Op.getStartLoc();
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!Diag) {
|
|
Diag = "invalid operand for instruction";
|
|
}
|
|
|
|
return Error(ErrorLoc, Diag);
|
|
}
|
|
|
|
bool M68kAsmParser::missingFeature(llvm::SMLoc const &Loc,
|
|
uint64_t const &ErrorInfo) {
|
|
return Error(Loc, "instruction requires a CPU feature not currently enabled");
|
|
}
|
|
|
|
bool M68kAsmParser::emit(MCInst &Inst, SMLoc const &Loc,
|
|
MCStreamer &Out) const {
|
|
Inst.setLoc(Loc);
|
|
Out.emitInstruction(Inst, STI);
|
|
|
|
return false;
|
|
}
|
|
|
|
bool M68kAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
|
|
OperandVector &Operands,
|
|
MCStreamer &Out,
|
|
uint64_t &ErrorInfo,
|
|
bool MatchingInlineAsm) {
|
|
MCInst Inst;
|
|
unsigned MatchResult =
|
|
MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
|
|
|
|
switch (MatchResult) {
|
|
case Match_Success:
|
|
return emit(Inst, Loc, Out);
|
|
case Match_MissingFeature:
|
|
return missingFeature(Loc, ErrorInfo);
|
|
case Match_InvalidOperand:
|
|
return invalidOperand(Loc, Operands, ErrorInfo);
|
|
case Match_MnemonicFail:
|
|
return Error(Loc, "invalid instruction");
|
|
default:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
void M68kOperand::print(raw_ostream &OS) const {
|
|
switch (Kind) {
|
|
case Kind::Invalid:
|
|
OS << "invalid";
|
|
break;
|
|
|
|
case Kind::Token:
|
|
OS << "token '" << Token << "'";
|
|
break;
|
|
|
|
case Kind::Imm:
|
|
OS << "immediate " << Imm;
|
|
break;
|
|
|
|
case Kind::MemOp:
|
|
MemOp.print(OS);
|
|
break;
|
|
}
|
|
}
|