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5c358e02ea
- For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". llvm-svn: 117519
24 lines
633 B
LLVM
24 lines
633 B
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
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define float @test(float %a, float %b) {
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entry:
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%0 = fdiv float %a, %b
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ret float %0
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}
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; VFP2: test:
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; VFP2: vdiv.f32 s0, s1, s0
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; NFP1: test:
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; NFP1: vdiv.f32 s0, s1, s0
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; NFP0: test:
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; NFP0: vdiv.f32 s0, s1, s0
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; CORTEXA8: test:
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; CORTEXA8: vdiv.f32 s0, s1, s0
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; CORTEXA9: test:
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; CORTEXA9: vdiv.f32 s0, s1, s0
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