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fa8f5fb2cf
compiled on mips32r1 processors because it uses synci and rdhwr instructions which are supported only on mips32r2, so I replaced this function with the call to function cacheflush which works for both mips32r1 and mips32r2. Patch by Sasa Stankovic llvm-svn: 141564
81 lines
2.4 KiB
C++
81 lines
2.4 KiB
C++
//===- Memory.cpp - Memory Handling Support ---------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines some helpful functions for allocating memory and dealing
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// with memory mapped files
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/Memory.h"
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#include "llvm/Support/Valgrind.h"
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#include "llvm/Config/config.h"
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#if defined(__mips__)
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#include <sys/cachectl.h>
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#endif
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namespace llvm {
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using namespace sys;
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}
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// Include the platform-specific parts of this class.
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#ifdef LLVM_ON_UNIX
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#include "Unix/Memory.inc"
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#endif
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#ifdef LLVM_ON_WIN32
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#include "Windows/Memory.inc"
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#endif
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extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
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/// InvalidateInstructionCache - Before the JIT can run a block of code
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/// that has been emitted it must invalidate the instruction cache on some
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/// platforms.
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void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
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size_t Len) {
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// icache invalidation for PPC and ARM.
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#if defined(__APPLE__)
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# if (defined(__POWERPC__) || defined (__ppc__) || \
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defined(_POWER) || defined(_ARCH_PPC)) || defined(__arm__)
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sys_icache_invalidate(Addr, Len);
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# endif
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#else
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# if (defined(__POWERPC__) || defined (__ppc__) || \
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defined(_POWER) || defined(_ARCH_PPC)) && defined(__GNUC__)
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const size_t LineSize = 32;
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const intptr_t Mask = ~(LineSize - 1);
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const intptr_t StartLine = ((intptr_t) Addr) & Mask;
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const intptr_t EndLine = ((intptr_t) Addr + Len + LineSize - 1) & Mask;
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for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
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asm volatile("dcbf 0, %0" : : "r"(Line));
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asm volatile("sync");
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for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
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asm volatile("icbi 0, %0" : : "r"(Line));
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asm volatile("isync");
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# elif defined(__arm__) && defined(__GNUC__)
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// FIXME: Can we safely always call this for __GNUC__ everywhere?
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char *Start = (char*) Addr;
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char *End = Start + Len;
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__clear_cache(Start, End);
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# elif defined(__mips__)
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cacheflush((char*)Addr, Len, BCACHE);
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# endif
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#endif // end apple
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ValgrindDiscardTranslations(Addr, Len);
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}
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