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register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. llvm-svn: 180969
42 lines
1.3 KiB
LLVM
42 lines
1.3 KiB
LLVM
; RUN: llc -march=mipsel -mattr=+dsp < %s
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@g1 = common global i64 0, align 8
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@g2 = common global i64 0, align 8
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@g3 = common global i64 0, align 8
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define i64 @test_acreg_copy(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
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entry:
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%0 = load i64* @g1, align 8
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%1 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a0, i32 %a1)
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%2 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a2, i32 %a3)
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store i64 %1, i64* @g1, align 8
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store i64 %2, i64* @g2, align 8
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tail call void @foo1()
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store i64 %2, i64* @g3, align 8
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ret i64 %1
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}
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declare i64 @llvm.mips.maddu(i64, i32, i32)
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declare void @foo1()
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@g4 = common global <2 x i16> zeroinitializer, align 4
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@g5 = common global <2 x i16> zeroinitializer, align 4
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@g6 = common global <2 x i16> zeroinitializer, align 4
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define { i32 } @test_ccond_spill(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%1 = bitcast i32 %b.coerce to <2 x i16>
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%cmp3 = icmp slt <2 x i16> %0, %1
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%sext = sext <2 x i1> %cmp3 to <2 x i16>
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store <2 x i16> %sext, <2 x i16>* @g4, align 4
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tail call void @foo1()
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%2 = load <2 x i16>* @g5, align 4
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%3 = load <2 x i16>* @g6, align 4
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%or = select <2 x i1> %cmp3, <2 x i16> %2, <2 x i16> %3
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%4 = bitcast <2 x i16> %or to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
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ret { i32 } %.fca.0.insert
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}
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