Kalle Raiskila 64680cd5b8 Change v64 datalayout in SPU. ... The SPU ABI does not mention v64, and all examples in C suggest v128 are treated similarily to arrays, we use array alignment for v64 too. This makes the alignment of e.g. [2 x <2 x i32>] behave "intuitively" and similar to as if the elements were e.g. i32s. This also makes an "unaligned store" test to be aligned, with different (but functionally equivalent) code generated. llvm-svn: 117360		2010-10-26 10:45:47 +00:00
..
Alpha
ARM	When the "true" and "false" blocks of a diamond if-conversion are the same,	2010-10-26 00:02:24 +00:00
Blackfin
CBackend
CellSPU	Change v64 datalayout in SPU.	2010-10-26 10:45:47 +00:00
CPP
Generic
MBlaze	Recommit 116986 with capitalization typo fixed.	2010-10-21 03:57:26 +00:00
Mips	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
MSP430	CombinerAA is now reordering these stores.	2010-09-20 20:56:29 +00:00
PowerPC	PowerPC varargs functions store live-in registers on the stack. Make sure we use	2010-10-11 20:43:09 +00:00
PTX	Add test case mov.ll for PTX device function	2010-10-19 13:21:51 +00:00
SPARC
SystemZ	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
Thumb	Try again to disable critical edge splitting in CodeGenPrepare.	2010-09-30 20:51:52 +00:00
Thumb2	More accurate estimate / tracking of register pressure.	2010-10-20 22:03:58 +00:00
X86	An stdcall function calling a non-stdcall function	2010-10-25 22:17:05 +00:00
XCore	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
thumb2-mul.ll	Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes	2010-09-21 22:51:46 +00:00