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662d042ab8
The RISC-V ISA defines RV32E as an alternative "base" instruction set encoding, that differs from RV32I by having only 16 rather than 32 registers. This patch adds basic definitions for RV32E as well as MC layer support (assembling, disassembling) and tests. The only supported ABI on RV32E is ILP32E. Add a new RISCVFeatures::validate() helper to RISCVUtils which can be called from codegen or MC layer libraries to validate the combination of TargetTriple and FeatureBitSet. Other targets have similar checks (e.g. erroring if SPE is enabled on PPC64 or oddspreg + o32 ABI on Mips), but they either duplicate the checks (Mips), or fail to check for both codegen and MC codepaths (PPC). Codegen for the ILP32E ABI support and RV32E codegen are left for a future patch/patches. Differential Revision: https://reviews.llvm.org/D59470 llvm-svn: 356744
330 lines
13 KiB
C++
330 lines
13 KiB
C++
//===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVDisassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "Utils/RISCVBaseInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class RISCVDisassembler : public MCDisassembler {
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public:
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RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createRISCVDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new RISCVDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeRISCVDisassembler() {
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// Register the disassembler for each target.
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TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
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createRISCVDisassembler);
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TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
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createRISCVDisassembler);
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}
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static const unsigned GPRDecoderTable[] = {
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RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3,
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RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7,
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RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11,
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RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
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RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19,
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RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23,
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RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27,
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RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31
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};
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static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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const FeatureBitset &FeatureBits =
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static_cast<const MCDisassembler *>(Decoder)
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->getSubtargetInfo()
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.getFeatureBits();
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bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
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if (RegNo > array_lengthof(GPRDecoderTable) || (IsRV32E && RegNo > 15))
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return MCDisassembler::Fail;
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// We must define our own mapping from RegNo to register identifier.
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// Accessing index RegNo in the register class will work in the case that
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// registers were added in ascending order, but not in general.
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unsigned Reg = GPRDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static const unsigned FPR32DecoderTable[] = {
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RISCV::F0_32, RISCV::F1_32, RISCV::F2_32, RISCV::F3_32,
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RISCV::F4_32, RISCV::F5_32, RISCV::F6_32, RISCV::F7_32,
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RISCV::F8_32, RISCV::F9_32, RISCV::F10_32, RISCV::F11_32,
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RISCV::F12_32, RISCV::F13_32, RISCV::F14_32, RISCV::F15_32,
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RISCV::F16_32, RISCV::F17_32, RISCV::F18_32, RISCV::F19_32,
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RISCV::F20_32, RISCV::F21_32, RISCV::F22_32, RISCV::F23_32,
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RISCV::F24_32, RISCV::F25_32, RISCV::F26_32, RISCV::F27_32,
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RISCV::F28_32, RISCV::F29_32, RISCV::F30_32, RISCV::F31_32
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};
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static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > array_lengthof(FPR32DecoderTable))
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return MCDisassembler::Fail;
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// We must define our own mapping from RegNo to register identifier.
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// Accessing index RegNo in the register class will work in the case that
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// registers were added in ascending order, but not in general.
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unsigned Reg = FPR32DecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 8) {
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return MCDisassembler::Fail;
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}
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unsigned Reg = FPR32DecoderTable[RegNo + 8];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static const unsigned FPR64DecoderTable[] = {
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RISCV::F0_64, RISCV::F1_64, RISCV::F2_64, RISCV::F3_64,
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RISCV::F4_64, RISCV::F5_64, RISCV::F6_64, RISCV::F7_64,
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RISCV::F8_64, RISCV::F9_64, RISCV::F10_64, RISCV::F11_64,
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RISCV::F12_64, RISCV::F13_64, RISCV::F14_64, RISCV::F15_64,
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RISCV::F16_64, RISCV::F17_64, RISCV::F18_64, RISCV::F19_64,
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RISCV::F20_64, RISCV::F21_64, RISCV::F22_64, RISCV::F23_64,
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RISCV::F24_64, RISCV::F25_64, RISCV::F26_64, RISCV::F27_64,
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RISCV::F28_64, RISCV::F29_64, RISCV::F30_64, RISCV::F31_64
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};
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static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > array_lengthof(FPR64DecoderTable))
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return MCDisassembler::Fail;
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// We must define our own mapping from RegNo to register identifier.
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// Accessing index RegNo in the register class will work in the case that
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// registers were added in ascending order, but not in general.
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unsigned Reg = FPR64DecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 8) {
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return MCDisassembler::Fail;
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}
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unsigned Reg = FPR64DecoderTable[RegNo + 8];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo == 0) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo == 2) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 8)
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return MCDisassembler::Fail;
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unsigned Reg = GPRDecoderTable[RegNo + 8];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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// Add implied SP operand for instructions *SP compressed instructions. The SP
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// operand isn't explicitly encoded in the instruction.
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static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
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if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
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Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
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Inst.getOpcode() == RISCV::C_FLWSP ||
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Inst.getOpcode() == RISCV::C_FSWSP ||
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Inst.getOpcode() == RISCV::C_FLDSP ||
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Inst.getOpcode() == RISCV::C_FSDSP ||
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Inst.getOpcode() == RISCV::C_ADDI4SPN) {
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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}
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if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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}
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}
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template <unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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addImplySP(Inst, Address, Decoder);
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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if (Imm == 0)
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return MCDisassembler::Fail;
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return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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addImplySP(Inst, Address, Decoder);
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// Sign-extend the number in the bottom N bits of Imm
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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if (Imm == 0)
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return MCDisassembler::Fail;
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return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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// Sign-extend the number in the bottom N bits of Imm after accounting for
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// the fact that the N bit immediate is stored in N-1 bits (the LSB is
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// always zero)
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<6>(Imm) && "Invalid immediate");
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if (Imm > 31) {
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Imm = (SignExtend64<6>(Imm) & 0xfffff);
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}
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<3>(Imm) && "Invalid immediate");
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if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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#include "RISCVGenDisassemblerTables.inc"
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DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &OS,
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raw_ostream &CS) const {
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// TODO: This will need modification when supporting instruction set
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// extensions with instructions > 32-bits (up to 176 bits wide).
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uint32_t Insn;
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DecodeStatus Result;
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// It's a 32 bit instruction if bit 0 and 1 are 1.
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if ((Bytes[0] & 0x3) == 0x3) {
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Insn = support::endian::read32le(Bytes.data());
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LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
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Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
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Size = 4;
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} else {
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if (Bytes.size() < 2) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Insn = support::endian::read16le(Bytes.data());
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if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
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LLVM_DEBUG(
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dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 2;
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return Result;
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}
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}
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LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
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Size = 2;
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}
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return Result;
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}
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