Justin Hibbits 668c53374d Complete the SPE instruction set patterns ... This is the lead-up to having SPE codegen. Add the rest of the instructions, along with MC tests. Differential Revision: https://reviews.llvm.org/D44829 llvm-svn: 337346		2018-07-18 04:24:57 +00:00
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AArch64	[AArch64][SVE]: Integer multiply-add/subtract instructions.	2018-07-17 15:41:58 +00:00
AMDGPU	[AMDGPU] Fix lit failures introduced in r335281	2018-06-21 22:30:09 +00:00
ARM	[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction	2018-07-06 08:03:12 +00:00
AsmParser	[X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104	2018-07-02 14:13:27 +00:00
AVR
BPF
COFF
Disassembler	Complete the SPE instruction set patterns	2018-07-18 04:24:57 +00:00
ELF	MC: Implement support for new .addrsig and .addrsig_sym directives.	2018-07-17 22:17:18 +00:00
Hexagon	[Hexagon] Fix the value of HexagonII::TypeCVI_FIRST	2018-06-19 18:09:54 +00:00
Lanai
MachO	[MC] Error on a .zerofill directive in a non-virtual section	2018-07-02 17:29:43 +00:00
Mips	[mips] Addition of the [d]rem and [d]remu instructions	2018-07-09 13:06:44 +00:00
PowerPC	Complete the SPE instruction set patterns	2018-07-18 04:24:57 +00:00
RISCV	[RISCV] Tail calls don't need to save return address	2018-06-21 14:37:09 +00:00
Sparc
SystemZ
WebAssembly	[WebAssembly] Remove ELF file support.	2018-07-16 23:09:29 +00:00
X86	[X86][AsmParser] Don't consider %eip as a valid register outside of 32-bit mode.	2018-07-03 17:40:51 +00:00