Simon Pilgrim 3fd222dafb [X86][SSE] Avoid unnecessary PMOVZX in v4i8 sum reduction ...

This should go away once D66004 has landed and we can simplify shuffle chains using demanded elts.

llvm-svn: 374658

2019-10-12 15:19:13 +00:00

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AArch64

Revert 374373: [Codegen] Alter the default promotion for saturating adds and subs

2019-10-11 20:33:03 +00:00

AMDGPU

[AMDGPU] Use GCN prefix in dpp_combine.mir. NFC.

2019-10-11 22:28:04 +00:00

ARC

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ARM

Revert 374373: [Codegen] Alter the default promotion for saturating adds and subs

2019-10-11 20:33:03 +00:00

AVR

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BPF

[BPF] Remove relocation for patchable externs

2019-10-10 15:33:09 +00:00

Generic

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Hexagon

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Inputs

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Lanai

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Mips

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MIR

Print quoted backslashes in LLVM IR as \\ instead of \5C

2019-10-10 18:31:57 +00:00

MSP430

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NVPTX

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PowerPC

[AIX] Use .space instead of .zero in assembly

2019-10-11 15:07:28 +00:00

RISCV

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SPARC

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SystemZ

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Thumb

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Thumb2

[ARM] VQSUB instruction

2019-10-10 16:34:30 +00:00

WebAssembly

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WinCFGuard

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WinEH

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X86

[X86][SSE] Avoid unnecessary PMOVZX in v4i8 sum reduction

2019-10-12 15:19:13 +00:00

XCore

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