Craig Topper 4581267dc8 [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16. ... The 0x63 opcodes in 64-bit mode have a fixed source size of 32-bits, but the destination size is controlled by REX.W and the 0x66 opsize prefix. This instruction is normally used with a REX.W prefix which provides desired behavior. The other encodings are interpretted as valid by the processor, but aren't useful. This patch makes us recognize them for the disassembler to match objdump. llvm-svn: 343614		2018-10-02 18:16:19 +00:00
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AArch64	[AArch64][v8.5A] Add Memory Tagging instructions	2018-10-02 10:04:39 +00:00
AMDGPU	AMDGPU: Fix v_dot{4, 8}* instruction encoding	2018-05-15 19:32:47 +00:00
ARC	[ARC] Prevent InstPrinter from crashing on unknown condition codes.	2018-09-06 19:58:26 +00:00
ARM	[ARM][v8.5A] Add speculation barriers SSBB and PSSBB	2018-09-28 08:27:56 +00:00
Hexagon	NFC - Various typo fixes in tests	2018-07-04 13:28:39 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips] Add missing instructions	2018-08-29 11:35:03 +00:00
PowerPC	Complete the SPE instruction set patterns	2018-07-18 04:24:57 +00:00
RISCV	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
WebAssembly	[WebAssembly] v8x16.shuffle	2018-09-07 21:54:46 +00:00
X86	[X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16.	2018-10-02 18:16:19 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00