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https://github.com/RPCS3/llvm-mirror.git
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dd3a5d8e78
llvm-svn: 150773
392 lines
13 KiB
C++
392 lines
13 KiB
C++
//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// MachineScheduler schedules machine instructions after phi elimination. It
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// preserves LiveIntervals so it can be invoked before register allocation.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "misched"
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#include "ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachinePassRegistry.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/OwningPtr.h"
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#include <queue>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Machine Instruction Scheduling Pass and Registry
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//===----------------------------------------------------------------------===//
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namespace {
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/// MachineScheduler runs after coalescing and before register allocation.
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class MachineScheduler : public MachineFunctionPass {
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public:
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const MachineLoopInfo *MLI;
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const MachineDominatorTree *MDT;
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LiveIntervals *LIS;
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MachineScheduler();
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory() {}
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virtual bool runOnMachineFunction(MachineFunction&);
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virtual void print(raw_ostream &O, const Module* = 0) const;
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static char ID; // Class identification, replacement for typeinfo
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};
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} // namespace
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char MachineScheduler::ID = 0;
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char &llvm::MachineSchedulerID = MachineScheduler::ID;
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INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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MachineScheduler::MachineScheduler()
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: MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
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initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
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}
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void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<AliasAnalysis>();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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namespace {
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/// MachineSchedRegistry provides a selection of available machine instruction
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/// schedulers.
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class MachineSchedRegistry : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineScheduler *);
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// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
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typedef ScheduleDAGCtor FunctionPassCtor;
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static MachinePassRegistry Registry;
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MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
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: MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
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Registry.Add(this);
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}
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~MachineSchedRegistry() { Registry.Remove(this); }
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// Accessors.
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//
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MachineSchedRegistry *getNext() const {
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return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
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}
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static MachineSchedRegistry *getList() {
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return (MachineSchedRegistry *)Registry.getList();
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}
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static ScheduleDAGCtor getDefault() {
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return (ScheduleDAGCtor)Registry.getDefault();
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}
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static void setDefault(ScheduleDAGCtor C) {
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Registry.setDefault((MachinePassCtor)C);
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}
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static void setListener(MachinePassRegistryListener *L) {
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Registry.setListener(L);
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}
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};
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} // namespace
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MachinePassRegistry MachineSchedRegistry::Registry;
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P);
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/// MachineSchedOpt allows command line selection of the scheduler.
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static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
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RegisterPassParser<MachineSchedRegistry> >
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MachineSchedOpt("misched",
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cl::init(&createDefaultMachineSched), cl::Hidden,
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cl::desc("Machine instruction scheduler to use"));
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//===----------------------------------------------------------------------===//
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// Machine Instruction Scheduling Common Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// ScheduleTopDownLive is an implementation of ScheduleDAGInstrs that schedules
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/// machine instructions while updating LiveIntervals.
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class ScheduleTopDownLive : public ScheduleDAGInstrs {
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protected:
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MachineScheduler *Pass;
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public:
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ScheduleTopDownLive(MachineScheduler *P):
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ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
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/// ScheduleDAGInstrs callback.
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void Schedule();
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/// Interface implemented by the selected top-down liveinterval scheduler.
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///
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/// Pick the next node to schedule, or return NULL.
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virtual SUnit *pickNode() = 0;
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/// When all preceeding dependencies have been resolved, free this node for
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/// scheduling.
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virtual void releaseNode(SUnit *SU) = 0;
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protected:
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSuccessors(SUnit *SU);
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};
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} // namespace
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
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/// NumPredsLeft reaches zero, release the successor node.
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void ScheduleTopDownLive::releaseSucc(SUnit *SU, SDep *SuccEdge) {
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SUnit *SuccSU = SuccEdge->getSUnit();
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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SuccSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--SuccSU->NumPredsLeft;
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if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
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releaseNode(SuccSU);
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}
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/// releaseSuccessors - Call releaseSucc on each of SU's successors.
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void ScheduleTopDownLive::releaseSuccessors(SUnit *SU) {
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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releaseSucc(SU, &*I);
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}
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}
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void ScheduleTopDownLive::Schedule() {
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BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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// Release any successors of the special Entry node. It is currently unused,
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// but we keep up appearances.
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releaseSuccessors(&EntrySU);
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// Release all DAG roots for scheduling.
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for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
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I != E; ++I) {
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// A SUnit is ready to schedule if it has no predecessors.
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if (I->Preds.empty())
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releaseNode(&(*I));
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}
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InsertPos = Begin;
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while (SUnit *SU = pickNode()) {
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DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
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// Move the instruction to its new location in the instruction stream.
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MachineInstr *MI = SU->getInstr();
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if (&*InsertPos == MI)
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++InsertPos;
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else {
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BB->splice(InsertPos, BB, MI);
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Pass->LIS->handleMove(MI);
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if (Begin == InsertPos)
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Begin = MI;
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}
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// Release dependent instructions for scheduling.
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releaseSuccessors(SU);
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}
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}
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bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
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// Initialize the context of the pass.
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MF = &mf;
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MLI = &getAnalysis<MachineLoopInfo>();
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MDT = &getAnalysis<MachineDominatorTree>();
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LIS = &getAnalysis<LiveIntervals>();
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TII = MF->getTarget().getInstrInfo();
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// Select the scheduler, or set the default.
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MachineSchedRegistry::ScheduleDAGCtor Ctor =
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MachineSchedRegistry::getDefault();
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if (!Ctor) {
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Ctor = MachineSchedOpt;
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MachineSchedRegistry::setDefault(Ctor);
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}
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// Instantiate the selected scheduler.
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OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
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// Visit all machine basic blocks.
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for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
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MBB != MBBEnd; ++MBB) {
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// Break the block into scheduling regions [I, RegionEnd), and schedule each
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// region as soon as it is discovered.
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unsigned RemainingCount = MBB->size();
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for(MachineBasicBlock::iterator RegionEnd = MBB->end();
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RegionEnd != MBB->begin();) {
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// The next region starts above the previous region. Look backward in the
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// instruction stream until we find the nearest boundary.
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MachineBasicBlock::iterator I = RegionEnd;
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for(;I != MBB->begin(); --I, --RemainingCount) {
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if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
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break;
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}
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if (I == RegionEnd) {
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// Skip empty scheduling regions.
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RegionEnd = llvm::prior(RegionEnd);
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--RemainingCount;
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continue;
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}
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// Skip regions with one instruction.
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if (I == llvm::prior(RegionEnd)) {
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RegionEnd = llvm::prior(RegionEnd);
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continue;
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}
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DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
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<< ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: ";
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if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
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else dbgs() << "End";
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dbgs() << " Remaining: " << RemainingCount << "\n");
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// Inform ScheduleDAGInstrs of the region being scheduled. It calls back
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// to our Schedule() method.
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Scheduler->Run(MBB, I, RegionEnd, MBB->size());
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RegionEnd = Scheduler->Begin;
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}
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assert(RemainingCount == 0 && "Instruction count mismatch!");
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}
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return true;
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}
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void MachineScheduler::print(raw_ostream &O, const Module* m) const {
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// unimplemented
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}
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//===----------------------------------------------------------------------===//
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// Placeholder for extending the machine instruction scheduler.
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//===----------------------------------------------------------------------===//
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namespace {
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class DefaultMachineScheduler : public ScheduleDAGInstrs {
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MachineScheduler *Pass;
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public:
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DefaultMachineScheduler(MachineScheduler *P):
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ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void Schedule();
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};
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} // namespace
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P) {
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return new DefaultMachineScheduler(P);
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}
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static MachineSchedRegistry
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SchedDefaultRegistry("default", "Activate the scheduler pass, "
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"but don't reorder instructions",
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createDefaultMachineSched);
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void DefaultMachineScheduler::Schedule() {
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BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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// TODO: Put interesting things here.
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//
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// When this is fully implemented, it will become a subclass of
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// ScheduleTopDownLive. So this driver will disappear.
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}
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//===----------------------------------------------------------------------===//
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// Machine Instruction Shuffler for Correctness Testing
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//===----------------------------------------------------------------------===//
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#ifndef NDEBUG
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namespace {
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// Nodes with a higher number have lower priority. This way we attempt to
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// schedule the latest instructions earliest.
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//
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// TODO: Relies on the property of the BuildSchedGraph that results in SUnits
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// being ordered in sequence bottom-up. This will be formalized, probably be
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// constructing SUnits in a prepass.
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struct ShuffleSUnitOrder {
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bool operator()(SUnit *A, SUnit *B) const {
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return A->NodeNum > B->NodeNum;
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}
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};
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/// Reorder instructions as much as possible.
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class InstructionShuffler : public ScheduleTopDownLive {
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std::priority_queue<SUnit*, std::vector<SUnit*>, ShuffleSUnitOrder> Queue;
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public:
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InstructionShuffler(MachineScheduler *P):
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ScheduleTopDownLive(P) {}
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/// ScheduleTopDownLive Interface
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virtual SUnit *pickNode() {
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if (Queue.empty()) return NULL;
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SUnit *SU = Queue.top();
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Queue.pop();
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return SU;
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}
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virtual void releaseNode(SUnit *SU) {
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Queue.push(SU);
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}
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};
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} // namespace
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static ScheduleDAGInstrs *createInstructionShuffler(MachineScheduler *P) {
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return new InstructionShuffler(P);
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}
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static MachineSchedRegistry ShufflerRegistry("shuffle",
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"Shuffle machine instructions",
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createInstructionShuffler);
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#endif // !NDEBUG
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