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https://github.com/RPCS3/llvm-mirror.git
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c168815f4b
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
263 lines
8.6 KiB
LLVM
263 lines
8.6 KiB
LLVM
; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32
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; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32
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; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R6
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; RUN: llc -march=mips -mcpu=mips32 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
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; RUN: llc -march=mips -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64
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; RUN: llc -march=mips -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64
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; RUN: llc -march=mips -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64R6
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; FIXME: The MIPS16 test should check its output
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; RUN: llc -march=mips -mattr=mips16 < %s
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; ALL-LABEL: madd1:
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; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
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; 32-DAG: mtlo $6
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; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
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; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31
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; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
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; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
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; 64-DAG: daddu $2, $[[T2]], $[[T3]]
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; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
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; 64R6-DAG: daddu $2, $[[T2]], $[[T3]]
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define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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%conv2 = sext i32 %b to i64
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%mul = mul nsw i64 %conv2, %conv
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%conv4 = sext i32 %c to i64
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%add = add nsw i64 %mul, %conv4
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ret i64 %add
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}
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; ALL-LABEL: madd2:
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; FIXME: We don't really need this instruction
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; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; 32-DAG: mtlo $6
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; 32-DAG: [[m:m]]addu ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: maddu $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
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; FIXME: There's a redundant move here. We should remove it
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; 32R6-DAG: muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $2, $[[T3]], $[[T2]]
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; 64-DAG: d[[m:m]]ult $5, $4
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; 64-DAG: [[m]]flo $[[T0:[0-9]+]]
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; 64-DAG: daddu $2, $[[T0]], $6
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; 64R6-DAG: dmul $[[T0:[0-9]+]], $5, $4
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; 64R6-DAG: daddu $2, $[[T0]], $6
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define i64 @madd2(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c) nounwind readnone {
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entry:
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%conv = zext i32 %a to i64
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%conv2 = zext i32 %b to i64
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%mul = mul nsw i64 %conv2, %conv
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%conv4 = zext i32 %c to i64
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%add = add nsw i64 %mul, %conv4
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ret i64 %add
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}
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; ALL-LABEL: madd3:
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; 32-DAG: mthi $6
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; 32-DAG: mtlo $7
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; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: mthi $[[AC:ac[0-3]+]], $6
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; DSP-DAG: mtlo $[[AC]], $7
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; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $7
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $7
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; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $6
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; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
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; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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; 64-DAG: daddu $2, $[[T2]], $6
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; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; 64R6-DAG: daddu $2, $[[T2]], $6
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define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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%conv2 = sext i32 %b to i64
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%mul = mul nsw i64 %conv2, %conv
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%add = add nsw i64 %mul, %c
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ret i64 %add
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}
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; ALL-LABEL: msub1:
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; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
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; 32-DAG: mtlo $6
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; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: sltu $[[T3:[0-9]+]], $6, $[[T1]]
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; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T3]], $[[T0]]
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; 32R6-DAG: sra $[[T5:[0-9]+]], $6, 31
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; 32R6-DAG: subu $2, $[[T5]], $[[T4]]
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; 32R6-DAG: subu $3, $6, $[[T1]]
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; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
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; 64-DAG: dsubu $2, $[[T3]], $[[T2]]
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; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
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; 64R6-DAG: dsubu $2, $[[T3]], $[[T2]]
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define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = sext i32 %c to i64
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%conv2 = sext i32 %a to i64
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%conv4 = sext i32 %b to i64
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%mul = mul nsw i64 %conv4, %conv2
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%sub = sub nsw i64 %conv, %mul
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ret i64 %sub
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}
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; ALL-LABEL: msub2:
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; FIXME: We don't really need this instruction
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; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; 32-DAG: mtlo $6
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; 32-DAG: [[m:m]]subu ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: msubu $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: muhu $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $6, $[[T1]]
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; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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; 32R6-DAG: negu $2, $[[T3]]
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; 32R6-DAG: subu $3, $6, $[[T1]]
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; 64-DAG: d[[m:m]]ult $5, $4
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; 64-DAG: [[m]]flo $[[T0:[0-9]+]]
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; 64-DAG: dsubu $2, $6, $[[T0]]
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; 64R6-DAG: dmul $[[T0:[0-9]+]], $5, $4
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; 64R6-DAG: dsubu $2, $6, $[[T0]]
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define i64 @msub2(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c) nounwind readnone {
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entry:
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%conv = zext i32 %c to i64
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%conv2 = zext i32 %a to i64
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%conv4 = zext i32 %b to i64
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%mul = mul nsw i64 %conv4, %conv2
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%sub = sub nsw i64 %conv, %mul
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ret i64 %sub
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}
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; ALL-LABEL: msub3:
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; FIXME: We don't really need this instruction
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; 32-DAG: mthi $6
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; 32-DAG: mtlo $7
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; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $7, $[[T1]]
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; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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; 32R6-DAG: subu $2, $6, $[[T3]]
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; 32R6-DAG: subu $3, $7, $[[T1]]
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; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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; 64-DAG: dsubu $2, $6, $[[T2]]
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; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; 64R6-DAG: dsubu $2, $6, $[[T2]]
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define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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%conv3 = sext i32 %b to i64
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%mul = mul nsw i64 %conv3, %conv
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%sub = sub nsw i64 %c, %mul
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ret i64 %sub
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}
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