llvm-mirror/test/MC/Disassembler
Ulrich Weigand 13b8f9f9df [SystemZ] Add missing FP extension instructions
This completes assembler / disassembler support for all BFP
instructions provided by the floating-point extensions facility.
The instructions added here are not currently used for codegen.

llvm-svn: 286285
2016-11-08 20:18:41 +00:00
..
AArch64 AArch64: TableGenerate system instruction operands. 2016-07-05 21:23:04 +00:00
AMDGPU [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. 2016-10-31 16:07:39 +00:00
ARM [ARM] Saturation instructions are DSP-only 2016-07-25 22:25:25 +00:00
Hexagon [Hexagon] Treat all conditional branches as predicted (not-taken by default) 2016-05-09 18:22:07 +00:00
Lanai
Mips [mips] Fix aui/daui/dahi/dati for MIPSR6 2016-10-14 09:31:42 +00:00
PowerPC [PPC] add absolute difference altivec instructions and matching intrinsics 2016-10-31 19:47:52 +00:00
Sparc
SystemZ [SystemZ] Add missing FP extension instructions 2016-11-08 20:18:41 +00:00
X86 Add new flag and intrinsic support for MWAITX and MONITORX instructions 2016-05-18 11:59:12 +00:00
XCore