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Arnaud A. de Grandmaison d8693073cb [EarlyCSE] Fix handling of target memory intrinsics for CSE'ing loads.

Summary:
Some target intrinsics can access multiple elements, using the pointer as a
base address (e.g. AArch64 ld4). When trying to CSE such instructions,
it must be checked the available value comes from a compatible instruction
because the pointer is not enough to discriminate whether the value is
correct.

Reviewers: ssijaric

Subscribers: mcrosier, llvm-commits, aemerson

Differential Revision: http://reviews.llvm.org/D13475

llvm-svn: 249523

2015-10-07 07:41:29 +00:00

AArch64

[EarlyCSE] Fix handling of target memory intrinsics for CSE'ing loads.

2015-10-07 07:41:29 +00:00

basic.ll

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00

commute.ll

…

conditional.ll

Extend EarlyCSE to handle basic cases from JumpThreading and CVP

2015-05-22 23:53:24 +00:00