Arnaud A. de Grandmaison d8693073cb [EarlyCSE] Fix handling of target memory intrinsics for CSE'ing loads. ...

Summary:
Some target intrinsics can access multiple elements, using the pointer as a
base address (e.g. AArch64 ld4). When trying to CSE such instructions,
it must be checked the available value comes from a compatible instruction
because the pointer is not enough to discriminate whether the value is
correct.

Reviewers: ssijaric

Subscribers: mcrosier, llvm-commits, aemerson

Differential Revision: http://reviews.llvm.org/D13475

llvm-svn: 249523

2015-10-07 07:41:29 +00:00

..

AArch64

[EarlyCSE] Fix handling of target memory intrinsics for CSE'ing loads.

2015-10-07 07:41:29 +00:00

basic.ll

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00

commute.ll

Update Transforms tests to use CHECK-LABEL for easier debugging. No functionality change.

2013-07-14 01:42:54 +00:00

conditional.ll

Extend EarlyCSE to handle basic cases from JumpThreading and CVP

2015-05-22 23:53:24 +00:00

edge.ll

Correct a mistaken comment from 238071 [NFC]

2015-05-23 00:05:43 +00:00

fence.ll

Allow value forwarding past release fences in EarlyCSE

2015-08-27 01:32:33 +00:00

floatingpoint.ll

Initially forgotten-to-svn-add test case for r177279.

2013-03-18 12:07:24 +00:00

instsimplify-dom.ll

Catch more CHECK that can be converted to CHECK-LABEL in Transforms for easier debugging. No functionality change.

2013-07-14 01:50:49 +00:00

read-reg.ll

Preserve the order of READ_REGISTER and WRITE_REGISTER

2015-05-18 16:42:10 +00:00