Matt Arsenault 2724c8cef5 AMDGPU: Don't rely on m0 being -1 for GWS offsets ...

This only works if the high bits of m0 are also 0, so m0 would have to
be set to 0xffff.

llvm-svn: 366608

2019-07-19 20:01:24 +00:00

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Analysis

[SCEV] add no wrap flag for SCEVAddExpr.

2019-07-18 09:23:19 +00:00

Assembler

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Bindings

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Bitcode

ARM MTE stack sanitizer.

2019-07-15 20:02:23 +00:00

BugPoint

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CodeGen

AMDGPU: Don't rely on m0 being -1 for GWS offsets

2019-07-19 20:01:24 +00:00

DebugInfo

[DebugInfo] Some fields do not need relocations even relax is enabled.

2019-07-19 06:10:36 +00:00

Demangle

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Examples

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ExecutionEngine

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Feature

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FileCheck

[FileCheck] Fix numeric variable redefinition

2019-07-18 13:39:04 +00:00

Instrumentation

hwasan: Initialize the pass only once.

2019-07-17 21:45:19 +00:00

Integer

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JitListener

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Linker

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LTO

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MachineVerifier

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MC

[RISCV] Disable tests failing on buildbots.

2019-07-19 18:05:12 +00:00

Object

[Object/llvm-readelf/llvm-readobj] - Improve error reporting when e_shstrndx is broken.

2019-07-16 11:07:30 +00:00

ObjectYAML

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Other

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SafepointIRVerifier

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Support

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SymbolRewriter

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TableGen

[TableGen] Do not set ReadNone attribute on intrinsics with side effects

2019-07-17 10:53:13 +00:00

ThinLTO/X86

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tools

[llvm-lipo] Remove trailing whitespace. NFC

2019-07-19 17:19:57 +00:00

Transforms

[NFC][InstCombine] Tests for 'rem' formation from sub-of-mul-by-'div' (PR42673)

2019-07-19 11:29:18 +00:00

Unit

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Verifier

ARM: Fix missing immarg for space intrinsic

2019-07-16 22:41:38 +00:00

YAMLParser

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.clang-format

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CMakeLists.txt

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lit.cfg.py

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lit.site.cfg.py.in

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TestRunner.sh

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