This website requires JavaScript.
Explore
Help
Register
Sign In
RPCS3
/
llvm-mirror
Watch
1
Star
0
Fork
0
You've already forked llvm-mirror
mirror of
https://github.com/RPCS3/llvm-mirror.git
synced
2025-02-06 20:27:42 +00:00
Code
Issues
Actions
Packages
Projects
Releases
Wiki
Activity
llvm-mirror
/
test
/
CodeGen
History
Evan Cheng
7cd6bfe549
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
...
llvm-svn: 91910
2009-12-22 17:47:23 +00:00
..
Alpha
…
ARM
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
2009-12-18 01:03:29 +00:00
Blackfin
…
CBackend
…
CellSPU
Revert this dag combine change:
2009-12-17 00:40:05 +00:00
CPP
…
Generic
…
Mips
…
MSP430
Lower setcc branchless, if this is profitable.
2009-12-11 23:01:29 +00:00
PIC16
While converting one of the operands to a memory operand, we need to check if it is Legal and does not result into a cyclic dep.
2009-12-22 14:25:37 +00:00
PowerPC
Do better with physical reg operands (typically, from inline asm)
2009-12-16 00:29:41 +00:00
SPARC
…
SystemZ
…
Thumb
Add test case for the phi reuse patch.
2009-12-18 00:11:44 +00:00
Thumb2
Make this test pass on Linux.
2009-12-16 07:35:25 +00:00
X86
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
2009-12-22 17:47:23 +00:00
XCore
…