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c80e71ac35
- Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. llvm-svn: 62664
42 lines
1.5 KiB
TableGen
42 lines
1.5 KiB
TableGen
//===--- SPU128InstrInfo.td - Cell SPU 128-bit operations -*- tablegen -*--===//
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//
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// Cell SPU 128-bit operations
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//
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//===----------------------------------------------------------------------===//
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// zext 32->128: Zero extend 32-bit to 128-bit
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def : Pat<(i128 (zext R32C:$rSrc)),
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(ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>;
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// zext 64->128: Zero extend 64-bit to 128-bit
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def : Pat<(i128 (zext R64C:$rSrc)),
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(ROTQMBYIr128_zext_r64 R64C:$rSrc, 8)>;
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// zext 16->128: Zero extend 16-bit to 128-bit
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def : Pat<(i128 (zext R16C:$rSrc)),
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(ROTQMBYIr128_zext_r32 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff)), 12)>;
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// zext 8->128: Zero extend 8-bit to 128-bit
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def : Pat<(i128 (zext R8C:$rSrc)),
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(ROTQMBYIr128_zext_r32 (ANDIi8i32 R8C:$rSrc, 0xf), 12)>;
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// anyext 32->128: Zero extend 32-bit to 128-bit
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def : Pat<(i128 (anyext R32C:$rSrc)),
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(ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>;
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// anyext 64->128: Zero extend 64-bit to 128-bit
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def : Pat<(i128 (anyext R64C:$rSrc)),
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(ROTQMBYIr128_zext_r64 R64C:$rSrc, 8)>;
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// anyext 16->128: Zero extend 16-bit to 128-bit
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def : Pat<(i128 (anyext R16C:$rSrc)),
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(ROTQMBYIr128_zext_r32 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff)), 12)>;
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// anyext 8->128: Zero extend 8-bit to 128-bit
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def : Pat<(i128 (anyext R8C:$rSrc)),
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(ROTQMBYIr128_zext_r32 (ANDIi8i32 R8C:$rSrc, 0xf), 12)>;
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// Shift left
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def : Pat<(shl GPRC:$rA, R32C:$rB),
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(SHLQBYBIr128 (SHLQBIr128 GPRC:$rA, R32C:$rB), R32C:$rB)>;
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