Tom Stellard 9454729563 AMDGPU/SI: Fix encoding of flat instructions on VI ...

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15735

llvm-svn: 256360

2015-12-24 03:18:18 +00:00

..

buffer_wbinv1l_vol_vi.s

AMDGPU: Add cache invalidation instructions.

2015-09-24 19:52:21 +00:00

ds-err.s

…

ds.s

…

flat-scratch.s

AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI

2015-12-21 18:44:27 +00:00

flat.s

AMDGPU/SI: Fix encoding of flat instructions on VI

2015-12-24 03:18:18 +00:00

hsa_code_object_isa_noargs.s

…

hsa-text.s

AMDGPU/SI: Use .hsatext section instead of .text for HSA

2015-09-25 21:41:28 +00:00

hsa.s

AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNEL

2015-11-06 11:45:14 +00:00

lit.local.cfg

…

mubuf.s

AMDGPU: Add cache invalidation instructions.

2015-09-24 19:52:21 +00:00

out-of-range-registers.s

AMDGPU: Fix asserts on invalid register ranges

2015-11-03 22:50:32 +00:00

smem.s

AMDGPU: Add s_dcache_* instructions

2015-09-24 19:52:27 +00:00

smrd-err.s

AMDGPU: Disallow s[102:103] on VI in assembler

2015-11-05 03:11:27 +00:00

smrd.s

AMDGPU: Fix asserts on invalid register ranges

2015-11-03 22:50:32 +00:00

sop1-err.s

AMDGPU: Disallow s[102:103] on VI in assembler

2015-11-05 03:11:27 +00:00

sop1.s

AMDGPU: Fix asserts on invalid register ranges

2015-11-03 22:50:32 +00:00

sop2.s

AMDGPU: Define correct number of SGPRs

2015-11-03 22:39:50 +00:00

sopc.s

…

sopk.s

…

sopp.s

…

vop1.s

AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp

2015-10-06 15:57:53 +00:00

vop2-err.s

AMDGPU/SI: Fix input vcc operand for VOP2b instructions

2015-09-08 21:15:00 +00:00

vop2.s

AMDGPU/SI: Fix input vcc operand for VOP2b instructions

2015-09-08 21:15:00 +00:00

vop3-errs.s

…

vop3-vop1-nosrc.s

AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp

2015-10-06 15:57:53 +00:00

vop3.s

AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp

2015-10-06 15:57:53 +00:00

vopc-errs.s

…

vopc.s

…