mirror of
https://github.com/RPCS3/llvm-mirror.git
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298f3fd9b7
to Instruction::mayWriteToMemory, fixing a FIXME, and helping various places that call mayWriteToMemory directly. llvm-svn: 40533
286 lines
8.8 KiB
C++
286 lines
8.8 KiB
C++
//===-- Instruction.cpp - Implement the Instruction class -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Instruction class for the VMCore library.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Type.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/Function.h"
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#include "llvm/Support/LeakDetector.h"
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using namespace llvm;
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Instruction::Instruction(const Type *ty, unsigned it, Use *Ops, unsigned NumOps,
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Instruction *InsertBefore)
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: User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) {
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// Make sure that we get added to a basicblock
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LeakDetector::addGarbageObject(this);
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// If requested, insert this instruction into a basic block...
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if (InsertBefore) {
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assert(InsertBefore->getParent() &&
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"Instruction to insert before is not in a basic block!");
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InsertBefore->getParent()->getInstList().insert(InsertBefore, this);
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}
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}
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Instruction::Instruction(const Type *ty, unsigned it, Use *Ops, unsigned NumOps,
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BasicBlock *InsertAtEnd)
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: User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) {
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// Make sure that we get added to a basicblock
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LeakDetector::addGarbageObject(this);
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// append this instruction into the basic block
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assert(InsertAtEnd && "Basic block to append to may not be NULL!");
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InsertAtEnd->getInstList().push_back(this);
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}
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// Out of line virtual method, so the vtable, etc has a home.
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Instruction::~Instruction() {
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assert(Parent == 0 && "Instruction still linked in the program!");
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}
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void Instruction::setParent(BasicBlock *P) {
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if (getParent()) {
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if (!P) LeakDetector::addGarbageObject(this);
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} else {
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if (P) LeakDetector::removeGarbageObject(this);
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}
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Parent = P;
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}
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void Instruction::removeFromParent() {
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getParent()->getInstList().remove(this);
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}
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void Instruction::eraseFromParent() {
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getParent()->getInstList().erase(this);
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}
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/// moveBefore - Unlink this instruction from its current basic block and
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/// insert it into the basic block that MovePos lives in, right before
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/// MovePos.
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void Instruction::moveBefore(Instruction *MovePos) {
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MovePos->getParent()->getInstList().splice(MovePos,getParent()->getInstList(),
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this);
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}
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const char *Instruction::getOpcodeName(unsigned OpCode) {
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switch (OpCode) {
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// Terminators
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case Ret: return "ret";
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case Br: return "br";
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case Switch: return "switch";
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case Invoke: return "invoke";
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case Unwind: return "unwind";
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case Unreachable: return "unreachable";
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// Standard binary operators...
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case Add: return "add";
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case Sub: return "sub";
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case Mul: return "mul";
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case UDiv: return "udiv";
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case SDiv: return "sdiv";
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case FDiv: return "fdiv";
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case URem: return "urem";
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case SRem: return "srem";
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case FRem: return "frem";
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// Logical operators...
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case And: return "and";
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case Or : return "or";
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case Xor: return "xor";
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// Memory instructions...
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case Malloc: return "malloc";
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case Free: return "free";
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case Alloca: return "alloca";
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case Load: return "load";
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case Store: return "store";
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case GetElementPtr: return "getelementptr";
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// Convert instructions...
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case Trunc: return "trunc";
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case ZExt: return "zext";
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case SExt: return "sext";
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case FPTrunc: return "fptrunc";
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case FPExt: return "fpext";
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case FPToUI: return "fptoui";
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case FPToSI: return "fptosi";
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case UIToFP: return "uitofp";
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case SIToFP: return "sitofp";
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case IntToPtr: return "inttoptr";
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case PtrToInt: return "ptrtoint";
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case BitCast: return "bitcast";
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// Other instructions...
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case ICmp: return "icmp";
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case FCmp: return "fcmp";
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case PHI: return "phi";
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case Select: return "select";
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case Call: return "call";
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case Shl: return "shl";
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case LShr: return "lshr";
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case AShr: return "ashr";
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case VAArg: return "va_arg";
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case ExtractElement: return "extractelement";
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case InsertElement: return "insertelement";
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case ShuffleVector: return "shufflevector";
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default: return "<Invalid operator> ";
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}
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return 0;
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}
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/// isIdenticalTo - Return true if the specified instruction is exactly
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/// identical to the current one. This means that all operands match and any
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/// extra information (e.g. load is volatile) agree.
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bool Instruction::isIdenticalTo(Instruction *I) const {
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if (getOpcode() != I->getOpcode() ||
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getNumOperands() != I->getNumOperands() ||
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getType() != I->getType())
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return false;
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// We have two instructions of identical opcode and #operands. Check to see
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// if all operands are the same.
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
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if (getOperand(i) != I->getOperand(i))
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return false;
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// Check special state that is a part of some instructions.
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if (const LoadInst *LI = dyn_cast<LoadInst>(this))
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return LI->isVolatile() == cast<LoadInst>(I)->isVolatile();
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if (const StoreInst *SI = dyn_cast<StoreInst>(this))
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return SI->isVolatile() == cast<StoreInst>(I)->isVolatile();
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if (const CmpInst *CI = dyn_cast<CmpInst>(this))
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return CI->getPredicate() == cast<CmpInst>(I)->getPredicate();
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if (const CallInst *CI = dyn_cast<CallInst>(this))
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return CI->isTailCall() == cast<CallInst>(I)->isTailCall();
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return true;
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}
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// isSameOperationAs
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bool Instruction::isSameOperationAs(Instruction *I) const {
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if (getOpcode() != I->getOpcode() || getType() != I->getType() ||
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getNumOperands() != I->getNumOperands())
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return false;
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// We have two instructions of identical opcode and #operands. Check to see
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// if all operands are the same type
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
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if (getOperand(i)->getType() != I->getOperand(i)->getType())
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return false;
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// Check special state that is a part of some instructions.
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if (const LoadInst *LI = dyn_cast<LoadInst>(this))
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return LI->isVolatile() == cast<LoadInst>(I)->isVolatile();
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if (const StoreInst *SI = dyn_cast<StoreInst>(this))
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return SI->isVolatile() == cast<StoreInst>(I)->isVolatile();
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if (const CmpInst *CI = dyn_cast<CmpInst>(this))
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return CI->getPredicate() == cast<CmpInst>(I)->getPredicate();
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if (const CallInst *CI = dyn_cast<CallInst>(this))
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return CI->isTailCall() == cast<CallInst>(I)->isTailCall();
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return true;
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}
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// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
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// have any side-effects or if it only reads memory.
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static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
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#define GET_SIDE_EFFECT_INFO
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#include "llvm/Intrinsics.gen"
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#undef GET_SIDE_EFFECT_INFO
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return false;
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}
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/// mayWriteToMemory - Return true if this instruction may modify memory.
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///
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bool Instruction::mayWriteToMemory() const {
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switch (getOpcode()) {
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default: return false;
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case Instruction::Free:
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case Instruction::Store:
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case Instruction::Invoke:
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case Instruction::VAArg:
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return true;
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case Instruction::Call:
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if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(this)) {
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// If the intrinsic doesn't write memory, it is safe.
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return !IntrinsicOnlyReadsMemory(II->getIntrinsicID());
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}
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return true;
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case Instruction::Load:
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return cast<LoadInst>(this)->isVolatile();
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}
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}
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/// isAssociative - Return true if the instruction is associative:
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///
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/// Associative operators satisfy: x op (y op z) === (x op y) op z)
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///
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/// In LLVM, the Add, Mul, And, Or, and Xor operators are associative, when not
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/// applied to floating point types.
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///
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bool Instruction::isAssociative(unsigned Opcode, const Type *Ty) {
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if (Opcode == And || Opcode == Or || Opcode == Xor)
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return true;
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// Add/Mul reassociate unless they are FP or FP vectors.
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if (Opcode == Add || Opcode == Mul)
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return !Ty->isFPOrFPVector();
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return 0;
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}
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/// isCommutative - Return true if the instruction is commutative:
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///
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/// Commutative operators satisfy: (x op y) === (y op x)
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///
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/// In LLVM, these are the associative operators, plus SetEQ and SetNE, when
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/// applied to any type.
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///
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bool Instruction::isCommutative(unsigned op) {
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switch (op) {
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case Add:
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case Mul:
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case And:
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case Or:
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case Xor:
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return true;
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default:
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return false;
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}
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}
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/// isTrappingInstruction - Return true if the instruction may trap.
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///
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bool Instruction::isTrapping(unsigned op) {
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switch(op) {
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case UDiv:
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case SDiv:
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case FDiv:
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case URem:
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case SRem:
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case FRem:
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case Load:
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case Store:
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case Call:
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case Invoke:
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return true;
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default:
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return false;
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}
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}
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