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e297a43f7c
This patch fixes register alignment for long double type in soft float mode. Before this patch alignment was 8 and this patch changes it to 4. Differential Revision: http://reviews.llvm.org/D18034 llvm-svn: 268909
21 lines
748 B
LLVM
21 lines
748 B
LLVM
; RUN: llc -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
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@x = global ppc_fp128 0xM405EDA5E353F7CEE0000000000000000, align 16
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@.str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1
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define void @foo() #0 {
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entry:
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%0 = load ppc_fp128, ppc_fp128* @x, align 16
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%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), ppc_fp128 %0)
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ret void
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}
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; Do not skip register r4 because of register alignment in soft float mode. Instead skipping
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; put in r4 part of first argument for printf function (long double).
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; CHECK: lwzu 4, x@l({{[0-9]+}})
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declare i32 @printf(i8* nocapture readonly, ...) #0
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attributes #0 = { "use-soft-float"="true" }
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