Nadav Rotem 8282fc9e3b Fix pr11266. ...

On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.

llvm-svn: 143311

2011-10-30 13:24:22 +00:00

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ARM

Always use the string pool, even when it makes the .o larger. This may help

2011-10-28 05:29:47 +00:00

CBackend

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CellSPU

Revert r143206, as there are still some failing tests.

2011-10-29 00:41:52 +00:00

CPP

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Generic

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MBlaze

Change the default scheduler from Latency to ILP, since Latency

2011-10-24 17:45:02 +00:00

Mips

Revert r143206, as there are still some failing tests.

2011-10-29 00:41:52 +00:00

MSP430

Remove the explicit request for "Latency" scheduling from MSP430,

2011-10-24 17:53:16 +00:00

PowerPC

test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now.

2011-10-28 23:11:03 +00:00

PTX

Change the default scheduler from Latency to ILP, since Latency

2011-10-24 17:45:02 +00:00

SPARC

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Thumb

Revert r143206, as there are still some failing tests.

2011-10-29 00:41:52 +00:00

Thumb2

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X86

Fix pr11266.

2011-10-30 13:24:22 +00:00

XCore

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