mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-07 11:51:13 +00:00
873c7239ab
This patch adds an experimental stage named MicroOpQueueStage. MicroOpQueueStage can be used to simulate a hardware micro-op queue (basically, a decoupling queue between 'decode' and 'dispatch'). Users can specify a queue size, as well as a optional MaxIPC (which - in the absence of a "Decoders" stage - can be used to simulate a different throughput from the decoders). This stage is added to the default pipeline between the EntryStage and the DispatchStage only if PipelineOption::MicroOpQueue is different than zero. By default, llvm-mca sets PipelineOption::MicroOpQueue to the value of hidden flag -micro-op-queue-size. Throughput from the decoder can be simulated via another hidden flag named -decoder-throughput. That flag allows us to quickly experiment with different frontend throughputs. For targets that declare a loop buffer, flag -decoder-throughput allows users to do multiple runs, each time simulating a different throughput from the decoders. This stage can/will be extended in future. For example, we could add a "buffer full" event to notify bottlenecks caused by backpressure. flag -decoder-throughput would probably go away if in future we delegate to another stage (DecoderStage?) the simulation of a (potentially variable) throughput from the decoders. For now, flag -decoder-throughput is "good enough" to run some simple experiments. Differential Revision: https://reviews.llvm.org/D59928 llvm-svn: 357248
70 lines
2.8 KiB
C++
70 lines
2.8 KiB
C++
//===---------------------------- Context.cpp -------------------*- C++ -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
/// \file
|
|
///
|
|
/// This file defines a class for holding ownership of various simulated
|
|
/// hardware units. A Context also provides a utility routine for constructing
|
|
/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
|
|
/// stages.
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/MCA/Context.h"
|
|
#include "llvm/MCA/HardwareUnits/RegisterFile.h"
|
|
#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
|
|
#include "llvm/MCA/HardwareUnits/Scheduler.h"
|
|
#include "llvm/MCA/Stages/DispatchStage.h"
|
|
#include "llvm/MCA/Stages/EntryStage.h"
|
|
#include "llvm/MCA/Stages/ExecuteStage.h"
|
|
#include "llvm/MCA/Stages/MicroOpQueueStage.h"
|
|
#include "llvm/MCA/Stages/RetireStage.h"
|
|
|
|
namespace llvm {
|
|
namespace mca {
|
|
|
|
std::unique_ptr<Pipeline>
|
|
Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
|
|
SourceMgr &SrcMgr) {
|
|
const MCSchedModel &SM = STI.getSchedModel();
|
|
|
|
// Create the hardware units defining the backend.
|
|
auto RCU = llvm::make_unique<RetireControlUnit>(SM);
|
|
auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
|
|
auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
|
|
Opts.StoreQueueSize, Opts.AssumeNoAlias);
|
|
auto HWS = llvm::make_unique<Scheduler>(SM, *LSU);
|
|
|
|
// Create the pipeline stages.
|
|
auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);
|
|
auto Dispatch = llvm::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
|
|
*RCU, *PRF);
|
|
auto Execute =
|
|
llvm::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
|
|
auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
|
|
|
|
// Pass the ownership of all the hardware units to this Context.
|
|
addHardwareUnit(std::move(RCU));
|
|
addHardwareUnit(std::move(PRF));
|
|
addHardwareUnit(std::move(LSU));
|
|
addHardwareUnit(std::move(HWS));
|
|
|
|
// Build the pipeline.
|
|
auto StagePipeline = llvm::make_unique<Pipeline>();
|
|
StagePipeline->appendStage(std::move(Fetch));
|
|
if (Opts.MicroOpQueueSize)
|
|
StagePipeline->appendStage(llvm::make_unique<MicroOpQueueStage>(
|
|
Opts.MicroOpQueueSize, Opts.DecodersThroughput));
|
|
StagePipeline->appendStage(std::move(Dispatch));
|
|
StagePipeline->appendStage(std::move(Execute));
|
|
StagePipeline->appendStage(std::move(Retire));
|
|
return StagePipeline;
|
|
}
|
|
|
|
} // namespace mca
|
|
} // namespace llvm
|