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2e17caf317
While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
490 lines
15 KiB
LLVM
490 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+tbm | FileCheck %s --check-prefix=GENERIC
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=bdver2 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=bdver3 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=bdver4 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER4
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define i32 @test_x86_tbm_bextri_u32(i32 %a0, i32* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_bextri_u32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
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; GENERIC-NEXT: # sched: [1:0.33]
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; GENERIC-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
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; GENERIC-NEXT: # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_bextri_u32:
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; BDVER: # %bb.0:
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; BDVER-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
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; BDVER-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
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; BDVER-NEXT: addl %ecx, %eax
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; BDVER-NEXT: retq
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%a1 = load i32, i32* %p1
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%r0 = lshr i32 %a0, 4
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%m0 = lshr i32 %a1, 4
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%r1 = and i32 %r0, 4095
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%m1 = and i32 %m0, 4095
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%res = add i32 %r1, %m1
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ret i32 %res
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}
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define i64 @test_x86_tbm_bextri_u64(i64 %a0, i64* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_bextri_u64:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
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; GENERIC-NEXT: # sched: [1:0.33]
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; GENERIC-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
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; GENERIC-NEXT: # sched: [5:0.50]
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_bextri_u64:
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; BDVER: # %bb.0:
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; BDVER-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
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; BDVER-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
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; BDVER-NEXT: addq %rcx, %rax
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; BDVER-NEXT: retq
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%a1 = load i64, i64* %p1
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%r0 = lshr i64 %a0, 4
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%m0 = lshr i64 %a1, 4
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%r1 = and i64 %r0, 4095
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%m1 = and i64 %m0, 4095
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%res = add i64 %r1, %m1
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ret i64 %res
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}
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define i32 @test_x86_tbm_blcfill_u32(i32 %a0, i32* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blcfill_u32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcfilll %edi, %ecx # sched: [1:0.33]
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; GENERIC-NEXT: blcfilll (%rsi), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blcfill_u32:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcfilll %edi, %ecx
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; BDVER-NEXT: blcfilll (%rsi), %eax
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; BDVER-NEXT: addl %ecx, %eax
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; BDVER-NEXT: retq
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%a1 = load i32, i32* %p1
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%r0 = add i32 %a0, 1
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%m0 = add i32 %a1, 1
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%r1 = and i32 %r0, %a0
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%m1 = and i32 %m0, %a1
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%res = add i32 %r1, %m1
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ret i32 %res
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}
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define i64 @test_x86_tbm_blcfill_u64(i64 %a0, i64* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blcfill_u64:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcfillq %rdi, %rcx # sched: [1:0.33]
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; GENERIC-NEXT: blcfillq (%rsi), %rax # sched: [5:0.50]
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blcfill_u64:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcfillq %rdi, %rcx
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; BDVER-NEXT: blcfillq (%rsi), %rax
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; BDVER-NEXT: addq %rcx, %rax
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; BDVER-NEXT: retq
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%a1 = load i64, i64* %p1
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%r0 = add i64 %a0, 1
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%m0 = add i64 %a1, 1
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%r1 = and i64 %r0, %a0
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%m1 = and i64 %m0, %a1
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%res = add i64 %r1, %m1
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ret i64 %res
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}
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define i32 @test_x86_tbm_blci_u32(i32 %a0, i32* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blci_u32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcil %edi, %ecx # sched: [1:0.33]
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; GENERIC-NEXT: blcil (%rsi), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blci_u32:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcil %edi, %ecx
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; BDVER-NEXT: blcil (%rsi), %eax
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; BDVER-NEXT: addl %ecx, %eax
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; BDVER-NEXT: retq
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%a1 = load i32, i32* %p1
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%r0 = add i32 1, %a0
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%m0 = add i32 1, %a1
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%r1 = xor i32 %r0, -1
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%m1 = xor i32 %m0, -1
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%r2 = or i32 %r1, %a0
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%m2 = or i32 %m1, %a1
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%res = add i32 %r2, %m2
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ret i32 %res
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}
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define i64 @test_x86_tbm_blci_u64(i64 %a0, i64* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blci_u64:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blciq %rdi, %rcx # sched: [1:0.33]
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; GENERIC-NEXT: blciq (%rsi), %rax # sched: [5:0.50]
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blci_u64:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blciq %rdi, %rcx
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; BDVER-NEXT: blciq (%rsi), %rax
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; BDVER-NEXT: addq %rcx, %rax
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; BDVER-NEXT: retq
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%a1 = load i64, i64* %p1
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%r0 = add i64 1, %a0
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%m0 = add i64 1, %a1
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%r1 = xor i64 %r0, -1
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%m1 = xor i64 %m0, -1
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%r2 = or i64 %r1, %a0
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%m2 = or i64 %m1, %a1
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%res = add i64 %r2, %m2
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ret i64 %res
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}
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define i32 @test_x86_tbm_blcic_u32(i32 %a0, i32* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blcic_u32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcicl %edi, %ecx # sched: [1:0.33]
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; GENERIC-NEXT: blcicl (%rsi), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blcic_u32:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcicl %edi, %ecx
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; BDVER-NEXT: blcicl (%rsi), %eax
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; BDVER-NEXT: addl %ecx, %eax
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; BDVER-NEXT: retq
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%a1 = load i32, i32* %p1
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%r0 = xor i32 %a0, -1
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%m0 = xor i32 %a1, -1
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%r1 = add i32 %a0, 1
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%m1 = add i32 %a1, 1
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%r2 = and i32 %r1, %r0
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%m2 = and i32 %m1, %m0
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%res = add i32 %r2, %m2
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ret i32 %res
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}
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define i64 @test_x86_tbm_blcic_u64(i64 %a0, i64* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blcic_u64:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcicq %rdi, %rcx # sched: [1:0.33]
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; GENERIC-NEXT: blcicq (%rsi), %rax # sched: [5:0.50]
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blcic_u64:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcicq %rdi, %rcx
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; BDVER-NEXT: blcicq (%rsi), %rax
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; BDVER-NEXT: addq %rcx, %rax
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; BDVER-NEXT: retq
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%a1 = load i64, i64* %p1
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%r0 = xor i64 %a0, -1
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%m0 = xor i64 %a1, -1
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%r1 = add i64 %a0, 1
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%m1 = add i64 %a1, 1
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%r2 = and i64 %r1, %r0
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%m2 = and i64 %m1, %m0
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%res = add i64 %r2, %m2
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ret i64 %res
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}
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define i32 @test_x86_tbm_blcmsk_u32(i32 %a0, i32* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blcmsk_u32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcmskl %edi, %ecx # sched: [1:0.33]
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; GENERIC-NEXT: blcmskl (%rsi), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blcmsk_u32:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcmskl %edi, %ecx
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; BDVER-NEXT: blcmskl (%rsi), %eax
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; BDVER-NEXT: addl %ecx, %eax
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; BDVER-NEXT: retq
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%a1 = load i32, i32* %p1
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%r0 = add i32 %a0, 1
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%m0 = add i32 %a1, 1
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%r1 = xor i32 %r0, %a0
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%m1 = xor i32 %m0, %a1
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%res = add i32 %r1, %m1
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ret i32 %res
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}
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define i64 @test_x86_tbm_blcmsk_u64(i64 %a0, i64* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blcmsk_u64:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcmskq %rdi, %rcx # sched: [1:0.33]
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; GENERIC-NEXT: blcmskq (%rsi), %rax # sched: [5:0.50]
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blcmsk_u64:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcmskq %rdi, %rcx
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; BDVER-NEXT: blcmskq (%rsi), %rax
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; BDVER-NEXT: addq %rcx, %rax
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; BDVER-NEXT: retq
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%a1 = load i64, i64* %p1
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%r0 = add i64 %a0, 1
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%m0 = add i64 %a1, 1
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%r1 = xor i64 %r0, %a0
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%m1 = xor i64 %m0, %a1
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%res = add i64 %r1, %m1
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ret i64 %res
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}
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define i32 @test_x86_tbm_blcs_u32(i32 %a0, i32* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blcs_u32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcsl %edi, %ecx # sched: [1:0.33]
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; GENERIC-NEXT: blcsl (%rsi), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blcs_u32:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcsl %edi, %ecx
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; BDVER-NEXT: blcsl (%rsi), %eax
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; BDVER-NEXT: addl %ecx, %eax
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; BDVER-NEXT: retq
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%a1 = load i32, i32* %p1
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%r0 = add i32 %a0, 1
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%m0 = add i32 %a1, 1
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%r1 = or i32 %r0, %a0
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%m1 = or i32 %m0, %a1
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%res = add i32 %r1, %m1
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ret i32 %res
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}
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define i64 @test_x86_tbm_blcs_u64(i64 %a0, i64* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blcs_u64:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blcsq %rdi, %rcx # sched: [1:0.33]
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; GENERIC-NEXT: blcsq (%rsi), %rax # sched: [5:0.50]
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blcs_u64:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blcsq %rdi, %rcx
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; BDVER-NEXT: blcsq (%rsi), %rax
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; BDVER-NEXT: addq %rcx, %rax
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; BDVER-NEXT: retq
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%a1 = load i64, i64* %p1
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%r0 = add i64 %a0, 1
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%m0 = add i64 %a1, 1
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%r1 = or i64 %r0, %a0
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%m1 = or i64 %m0, %a1
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%res = add i64 %r1, %m1
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ret i64 %res
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}
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define i32 @test_x86_tbm_blsfill_u32(i32 %a0, i32* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blsfill_u32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blsfilll %edi, %ecx # sched: [1:0.33]
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; GENERIC-NEXT: blsfilll (%rsi), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blsfill_u32:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blsfilll %edi, %ecx
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; BDVER-NEXT: blsfilll (%rsi), %eax
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; BDVER-NEXT: addl %ecx, %eax
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; BDVER-NEXT: retq
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%a1 = load i32, i32* %p1
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%r0 = add i32 %a0, -1
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%m0 = add i32 %a1, -1
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%r1 = or i32 %r0, %a0
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%m1 = or i32 %m0, %a1
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%res = add i32 %r1, %m1
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ret i32 %res
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}
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define i64 @test_x86_tbm_blsfill_u64(i64 %a0, i64* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blsfill_u64:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blsfillq %rdi, %rcx # sched: [1:0.33]
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; GENERIC-NEXT: blsfillq (%rsi), %rax # sched: [5:0.50]
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blsfill_u64:
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; BDVER: # %bb.0:
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; BDVER-NEXT: blsfillq %rdi, %rcx
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; BDVER-NEXT: blsfillq (%rsi), %rax
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; BDVER-NEXT: addq %rcx, %rax
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; BDVER-NEXT: retq
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%a1 = load i64, i64* %p1
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%r0 = add i64 %a0, -1
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%m0 = add i64 %a1, -1
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%r1 = or i64 %r0, %a0
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%m1 = or i64 %m0, %a1
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%res = add i64 %r1, %m1
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ret i64 %res
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}
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define i32 @test_x86_tbm_blsic_u32(i32 %a0, i32* nocapture %p1) nounwind {
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; GENERIC-LABEL: test_x86_tbm_blsic_u32:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: blsicl %edi, %ecx # sched: [1:0.33]
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; GENERIC-NEXT: blsicl (%rsi), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_x86_tbm_blsic_u32:
|
|
; BDVER: # %bb.0:
|
|
; BDVER-NEXT: blsicl %edi, %ecx
|
|
; BDVER-NEXT: blsicl (%rsi), %eax
|
|
; BDVER-NEXT: addl %ecx, %eax
|
|
; BDVER-NEXT: retq
|
|
%a1 = load i32, i32* %p1
|
|
%r0 = xor i32 %a0, -1
|
|
%m0 = xor i32 %a1, -1
|
|
%r1 = add i32 %a0, -1
|
|
%m1 = add i32 %a1, -1
|
|
%r2 = or i32 %r0, %r1
|
|
%m2 = or i32 %m0, %m1
|
|
%res = add i32 %r2, %m2
|
|
ret i32 %res
|
|
}
|
|
|
|
define i64 @test_x86_tbm_blsic_u64(i64 %a0, i64* nocapture %p1) nounwind {
|
|
; GENERIC-LABEL: test_x86_tbm_blsic_u64:
|
|
; GENERIC: # %bb.0:
|
|
; GENERIC-NEXT: blsicq %rdi, %rcx # sched: [1:0.33]
|
|
; GENERIC-NEXT: blsicq (%rsi), %rax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; BDVER-LABEL: test_x86_tbm_blsic_u64:
|
|
; BDVER: # %bb.0:
|
|
; BDVER-NEXT: blsicq %rdi, %rcx
|
|
; BDVER-NEXT: blsicq (%rsi), %rax
|
|
; BDVER-NEXT: addq %rcx, %rax
|
|
; BDVER-NEXT: retq
|
|
%a1 = load i64, i64* %p1
|
|
%r0 = xor i64 %a0, -1
|
|
%m0 = xor i64 %a1, -1
|
|
%r1 = add i64 %a0, -1
|
|
%m1 = add i64 %a1, -1
|
|
%r2 = or i64 %r0, %r1
|
|
%m2 = or i64 %m0, %m1
|
|
%res = add i64 %r2, %m2
|
|
ret i64 %res
|
|
}
|
|
|
|
define i32 @test_x86_tbm_t1mskc_u32(i32 %a0, i32* nocapture %p1) nounwind {
|
|
; GENERIC-LABEL: test_x86_tbm_t1mskc_u32:
|
|
; GENERIC: # %bb.0:
|
|
; GENERIC-NEXT: t1mskcl %edi, %ecx # sched: [1:0.33]
|
|
; GENERIC-NEXT: t1mskcl (%rsi), %eax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; BDVER-LABEL: test_x86_tbm_t1mskc_u32:
|
|
; BDVER: # %bb.0:
|
|
; BDVER-NEXT: t1mskcl %edi, %ecx
|
|
; BDVER-NEXT: t1mskcl (%rsi), %eax
|
|
; BDVER-NEXT: addl %ecx, %eax
|
|
; BDVER-NEXT: retq
|
|
%a1 = load i32, i32* %p1
|
|
%r0 = xor i32 %a0, -1
|
|
%m0 = xor i32 %a1, -1
|
|
%r1 = add i32 %a0, 1
|
|
%m1 = add i32 %a1, 1
|
|
%r2 = or i32 %r0, %r1
|
|
%m2 = or i32 %m0, %m1
|
|
%res = add i32 %r2, %m2
|
|
ret i32 %res
|
|
}
|
|
|
|
define i64 @test_x86_tbm_t1mskc_u64(i64 %a0, i64* nocapture %p1) nounwind {
|
|
; GENERIC-LABEL: test_x86_tbm_t1mskc_u64:
|
|
; GENERIC: # %bb.0:
|
|
; GENERIC-NEXT: t1mskcq %rdi, %rcx # sched: [1:0.33]
|
|
; GENERIC-NEXT: t1mskcq (%rsi), %rax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; BDVER-LABEL: test_x86_tbm_t1mskc_u64:
|
|
; BDVER: # %bb.0:
|
|
; BDVER-NEXT: t1mskcq %rdi, %rcx
|
|
; BDVER-NEXT: t1mskcq (%rsi), %rax
|
|
; BDVER-NEXT: addq %rcx, %rax
|
|
; BDVER-NEXT: retq
|
|
%a1 = load i64, i64* %p1
|
|
%r0 = xor i64 %a0, -1
|
|
%m0 = xor i64 %a1, -1
|
|
%r1 = add i64 %a0, 1
|
|
%m1 = add i64 %a1, 1
|
|
%r2 = or i64 %r0, %r1
|
|
%m2 = or i64 %m0, %m1
|
|
%res = add i64 %r2, %m2
|
|
ret i64 %res
|
|
}
|
|
|
|
define i32 @test_x86_tbm_tzmsk_u32(i32 %a0, i32* nocapture %p1) nounwind {
|
|
; GENERIC-LABEL: test_x86_tbm_tzmsk_u32:
|
|
; GENERIC: # %bb.0:
|
|
; GENERIC-NEXT: tzmskl %edi, %ecx # sched: [1:0.33]
|
|
; GENERIC-NEXT: tzmskl (%rsi), %eax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; BDVER-LABEL: test_x86_tbm_tzmsk_u32:
|
|
; BDVER: # %bb.0:
|
|
; BDVER-NEXT: tzmskl %edi, %ecx
|
|
; BDVER-NEXT: tzmskl (%rsi), %eax
|
|
; BDVER-NEXT: addl %ecx, %eax
|
|
; BDVER-NEXT: retq
|
|
%a1 = load i32, i32* %p1
|
|
%r0 = xor i32 %a0, -1
|
|
%m0 = xor i32 %a1, -1
|
|
%r1 = add i32 %a0, -1
|
|
%m1 = add i32 %a1, -1
|
|
%r2 = and i32 %r0, %r1
|
|
%m2 = and i32 %m0, %m1
|
|
%res = add i32 %r2, %m2
|
|
ret i32 %res
|
|
}
|
|
|
|
define i64 @test_x86_tbm_tzmsk_u64(i64 %a0, i64* nocapture %p1) nounwind {
|
|
; GENERIC-LABEL: test_x86_tbm_tzmsk_u64:
|
|
; GENERIC: # %bb.0:
|
|
; GENERIC-NEXT: tzmskq %rdi, %rcx # sched: [1:0.33]
|
|
; GENERIC-NEXT: tzmskq (%rsi), %rax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; BDVER-LABEL: test_x86_tbm_tzmsk_u64:
|
|
; BDVER: # %bb.0:
|
|
; BDVER-NEXT: tzmskq %rdi, %rcx
|
|
; BDVER-NEXT: tzmskq (%rsi), %rax
|
|
; BDVER-NEXT: addq %rcx, %rax
|
|
; BDVER-NEXT: retq
|
|
%a1 = load i64, i64* %p1
|
|
%r0 = xor i64 %a0, -1
|
|
%m0 = xor i64 %a1, -1
|
|
%r1 = add i64 %a0, -1
|
|
%m1 = add i64 %a1, -1
|
|
%r2 = and i64 %r0, %r1
|
|
%m2 = and i64 %m0, %m1
|
|
%res = add i64 %r2, %m2
|
|
ret i64 %res
|
|
}
|