llvm-mirror/test/MC/Mips/mips64r5/invalid-mips64.s
Vasileios Kalintiris 3e5853048c [mips] Added support for the ERETNC instruction.
Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

llvm-svn: 242666
2015-07-20 12:28:56 +00:00

9 lines
300 B
ArmAsm

# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled