mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-04 01:11:44 +00:00
51463c570e
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
23 lines
523 B
LLVM
23 lines
523 B
LLVM
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
|
|
; RUN: llvm-objdump -disassemble - | FileCheck %s
|
|
|
|
; Sign extend from 32 to 64 was creating nonsense opcodes
|
|
|
|
; CHECK: sll ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
|
|
|
|
define i64 @foo(i32 %ival) nounwind readnone {
|
|
entry:
|
|
%conv = sext i32 %ival to i64
|
|
ret i64 %conv
|
|
}
|
|
|
|
; CHECK-LABEL: foo_2:
|
|
; CHECK: dext ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0, 32
|
|
|
|
define i64 @foo_2(i32 %ival_2) nounwind readnone {
|
|
entry:
|
|
%conv_2 = zext i32 %ival_2 to i64
|
|
ret i64 %conv_2
|
|
}
|
|
|