Evan Cheng ed09135349 Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends ... was lowering them to sext / uxt + mul instructions. Unfortunately the optimization passes may hoist the extensions out of the loop and separate them. When that happens, the long multiplication instructions can be broken into several scalar instructions, causing significant performance issue. Note the vmla and vmls intrinsics are not added back. Frontend will codegen them as intrinsics vmull* + add / sub. Also note the isel optimizations for catching mul + sext / zext are not changed either. First part of rdar://8832507, rdar://9203134 llvm-svn: 128502		2011-03-29 23:06:19 +00:00
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2006-12-11-Cast-ConstExpr.ll
2009-06-11-FirstClassAggregateConstant.ll
AutoUpgradeGlobals.ll
AutoUpgradeGlobals.ll.bc
AutoUpgradeIntrinsics.ll
AutoUpgradeIntrinsics.ll.bc
dg.exp
extractelement.ll
flags.ll
memcpy.ll
metadata-2.ll
metadata.ll
neon-intrinsics.ll	Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends	2011-03-29 23:06:19 +00:00
neon-intrinsics.ll.bc
null-type.ll	Testcase for PR8494 (invalid bitcode crashing the bitcode reader).	2010-10-28 15:57:30 +00:00
null-type.ll.bc	Testcase for PR8494 (invalid bitcode crashing the bitcode reader).	2010-10-28 15:57:30 +00:00
sse2_loadl_pd.ll
sse2_loadl_pd.ll.bc
sse2_movl_dq.ll
sse2_movl_dq.ll.bc
sse2_movs_d.ll
sse2_movs_d.ll.bc
sse2_punpck_qdq.ll
sse2_punpck_qdq.ll.bc
sse2_shuf_pd.ll
sse2_shuf_pd.ll.bc
sse2_unpck_pd.ll
sse2_unpck_pd.ll.bc
sse41_pmulld.ll
sse41_pmulld.ll.bc
ssse3_palignr.ll
ssse3_palignr.ll.bc