Evan Cheng e31c929c2d DAGCombine's logic for forming pre- and post- indexed loads / stores were being
overly conservative. It was concerned about cases where it would prohibit
folding simple [r, c] addressing modes. e.g.
  ldr r0, [r2]
  ldr r1, [r2, #4]
=>
  ldr r0, [r2], #4
  ldr r1, [r2]
Change the logic to look for such cases which allows it to form indexed memory
ops more aggressively.

rdar://10674430

llvm-svn: 148086
2012-01-13 01:37:24 +00:00
..
2011-11-27 06:10:54 +00:00
2012-01-12 19:54:02 +00:00
2011-11-29 17:40:10 +00:00
2011-10-24 17:24:05 +00:00