llvm-mirror/test/CodeGen/AArch64/arm64-const-addr.ll
Evandro Menezes 5d88cb6cf6 [AArch64] Generate literals by the little end
ARM seems to prefer that long literals be formed from their little end in
order to promote the fusion of the instrs pairs MOV/MOVK and MOVK/MOVK on
Cortex A57 and others (v.  "Cortex A57 Software Optimisation Guide", section
4.14).

Differential revision: https://reviews.llvm.org/D28697

llvm-svn: 292422
2017-01-18 18:57:08 +00:00

24 lines
688 B
LLVM

; RUN: llc -mtriple=arm64-darwin-unknown < %s | FileCheck %s
%T = type { i32, i32, i32, i32 }
; Test if the constant base address gets only materialized once.
define i32 @test1() nounwind {
; CHECK-LABEL: test1
; CHECK: mov w8, #49152
; CHECK-NEXT: movk w8, #1039, lsl #16
; CHECK-NEXT: ldp w9, w10, [x8, #4]
; CHECK: ldr w8, [x8, #12]
%at = inttoptr i64 68141056 to %T*
%o1 = getelementptr %T, %T* %at, i32 0, i32 1
%t1 = load i32, i32* %o1
%o2 = getelementptr %T, %T* %at, i32 0, i32 2
%t2 = load i32, i32* %o2
%a1 = add i32 %t1, %t2
%o3 = getelementptr %T, %T* %at, i32 0, i32 3
%t3 = load i32, i32* %o3
%a2 = add i32 %a1, %t3
ret i32 %a2
}