llvm-mirror/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

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# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s
# CHECK: %1:gpr32common = ANDWri {{.*}}
# CHECK-NEXT: $wzr = SUBSWri {{.*}}
--- |
define i32 @test01() nounwind {
entry:
%0 = select i1 true, i32 1, i32 0
%1 = and i32 %0, 65535
%2 = icmp ugt i32 %1, 0
br i1 %2, label %if.then, label %if.end
if.then: ; preds = %entry
ret i32 1
if.end: ; preds = %entry
ret i32 0
}
...
---
name: test01
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32common }
body: |
bb.0.entry:
successors: %bb.2.if.end, %bb.1.if.then
%0 = MOVi32imm 1
%1 = ANDWri killed %1, 15
$wzr = SUBSWri killed %1, 0, 0, implicit-def $nzcv
Bcc 9, %bb.2.if.end, implicit $nzcv
bb.1.if.then:
$w0 = MOVi32imm 1
RET_ReallyLR implicit $w0
bb.2.if.end:
$w0 = MOVi32imm 0
RET_ReallyLR implicit $w0
...