llvm-mirror/test/CodeGen/AArch64/arm64-reserve-call-saved-reg.ll
Tri Vo ae0244420d [AArch64] Support adding X[8-15,18] registers as CSRs.
Summary:
Specifying X[8-15,18] registers as callee-saved is used to support
CONFIG_ARM64_LSE_ATOMICS in Linux kernel. As part of this patch we:
- use custom CSR list/mask when user specifies custom CSRs
- update Machine Register Info's list of CSRs with additional custom CSRs in
LowerCall and LowerFormalArguments.

Reviewers: srhines, nickdesaulniers, efriedma, javed.absar

Reviewed By: nickdesaulniers

Subscribers: kristof.beyls, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D52216

llvm-svn: 342824
2018-09-22 22:17:50 +00:00

29 lines
835 B
LLVM

; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x18 -mattr=+call-saved-x18 \
; RUN: -o - %s | FileCheck %s
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x18 -mattr=+call-saved-x18 \
; RUN: -global-isel \
; RUN: -o - %s | FileCheck %s
; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x18 -mattr=+call-saved-x18 \
; RUN: -fast-isel \
; RUN: -o - %s | FileCheck %s
; Used to exhaust the supply of GPRs.
@var = global [30 x i64] zeroinitializer
; If a register is specified to be both reserved and callee-saved, then it
; should not be allocated and should not be spilled onto the stack.
define void @foo() {
; CHECK-NOT: str x18, [sp
%val = load volatile [30 x i64], [30 x i64]* @var
store volatile [30 x i64] %val, [30 x i64]* @var
; CHECK-NOT: ldr x18
; CHECK-NOT: str x18
; CHECK-NOT: ldr x18, [sp
ret void
}