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5f32a8dbc4
Currently a vector move of 0 or -1 will use different instructions depending on the size of the vector. Using a single instruction (the 128-bit one) for both gives more opportunity for Machine CSE to eliminate instructions. Differential Revision: https://reviews.llvm.org/D53579 llvm-svn: 345270
28 lines
1.0 KiB
LLVM
28 lines
1.0 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s
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; PR23065: SCALAR_TO_VECTOR implies the top elements 1 to N-1 of the N-element vector are undefined.
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define <4 x i16> @foo1(<2 x i32> %a) {
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; CHECK-LABEL: foo1:
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; CHECK: movi v0.2d, #0000000000000000
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; CHECK-NEXT: ret
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%1 = shufflevector <2 x i32> <i32 58712, i32 undef>, <2 x i32> %a, <2 x i32> <i32 0, i32 2>
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; Can't optimize the following bitcast to scalar_to_vector.
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%2 = bitcast <2 x i32> %1 to <4 x i16>
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%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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ret <4 x i16> %3
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}
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define <4 x i16> @foo2(<2 x i32> %a) {
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; CHECK-LABEL: foo2:
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; CHECK: movi v0.2d, #0000000000000000
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; CHECK-NEXT: ret
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%1 = shufflevector <2 x i32> <i32 712, i32 undef>, <2 x i32> %a, <2 x i32> <i32 0, i32 2>
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; Can't optimize the following bitcast to scalar_to_vector.
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%2 = bitcast <2 x i32> %1 to <4 x i16>
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%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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ret <4 x i16> %3
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}
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