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31c3bd6557
This extends the existing transform for: add X, 0/1 --> sub X, 0/-1 ...to allow the sibling subtraction fold. This pattern could regress with the proposed change in D57401. llvm-svn: 352680
58 lines
1.5 KiB
LLVM
58 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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define <4 x i32> @sextbool_add_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
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; CHECK-LABEL: sextbool_add_vector:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
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; CHECK-NEXT: ret
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%c = icmp eq <4 x i32> %c1, %c2
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%b = sext <4 x i1> %c to <4 x i32>
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%s = add <4 x i32> %x, %b
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ret <4 x i32> %s
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}
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define <4 x i32> @zextbool_sub_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
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; CHECK-LABEL: zextbool_sub_vector:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
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; CHECK-NEXT: ret
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%c = icmp eq <4 x i32> %c1, %c2
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%b = zext <4 x i1> %c to <4 x i32>
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%s = sub <4 x i32> %x, %b
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ret <4 x i32> %s
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}
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define i32 @assertsext_sub_1(i1 signext %cond, i32 %y) {
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; CHECK-LABEL: assertsext_sub_1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w0, w1, w0
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; CHECK-NEXT: ret
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%e = zext i1 %cond to i32
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%r = sub i32 %y, %e
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ret i32 %r
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}
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define i32 @assertsext_add_1(i1 signext %cond, i32 %y) {
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; CHECK-LABEL: assertsext_add_1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w0, w1, w0
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; CHECK-NEXT: ret
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%e = zext i1 %cond to i32
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%r = add i32 %e, %y
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ret i32 %r
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}
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define i32 @assertsext_add_1_commute(i1 signext %cond, i32 %y) {
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; CHECK-LABEL: assertsext_add_1_commute:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w0, w1, w0
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; CHECK-NEXT: ret
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%e = zext i1 %cond to i32
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%r = add i32 %y, %e
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ret i32 %r
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}
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