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009fdea45c
ARMv8.1a CASP instructions need the first of the pair to be an even register (otherwise the encoding is unallocated). We enforced this during assembly, but not CodeGen before. llvm-svn: 353308
18 lines
863 B
LLVM
18 lines
863 B
LLVM
; RUN: llc -mtriple arm64-apple-ios -mattr=+lse %s -o - | FileCheck %s
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; Only "even,even+1" pairs are valid for CASP instructions. Make sure LLVM
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; doesn't allocate odd ones and that it can copy them around properly. N.b. we
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; don't actually check that they're sequential because FileCheck can't; odd/even
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; will have to be good enough.
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define void @test_atomic_cmpxchg_i128_register_shuffling(i128* %addr, i128 %desired, i128 %new) nounwind {
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; CHECK-LABEL: test_atomic_cmpxchg_i128_register_shuffling:
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; CHECK-DAG: mov [[DESIRED_LO:x[0-9]*[02468]]], x1
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; CHECK-DAG: mov [[DESIRED_HI:x[0-9]*[13579]]], x2
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; CHECK-DAG: mov [[NEW_LO:x[0-9]*[02468]]], x3
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; CHECK-DAG: mov [[NEW_HI:x[0-9]*[13579]]], x4
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; CHECK: caspal [[DESIRED_LO]], [[DESIRED_HI]], [[NEW_LO]], [[NEW_HI]], [x0]
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%res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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ret void
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}
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