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17a3580afc
The bug is visible in the constant-folded x86 tests. We can't use the negated shift amount when the type is not power-of-2: https://rise4fun.com/Alive/US1r ...so in that case, use the regular lowering that includes a select to guard against a shift-by-bitwidth. This path is improved by only calculating the modulo shift amount once now. Also, improve the rotate (with power-of-2 size) lowering to use a negate rather than subtract from bitwidth. This improves the codegen whether we have a rotate instruction or not (although we can still see that we're not matching to a legal rotate in all cases). llvm-svn: 338592
304 lines
8.5 KiB
LLVM
304 lines
8.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i8 @llvm.fshl.i8(i8, i8, i8)
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declare i16 @llvm.fshl.i16(i16, i16, i16)
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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declare i8 @llvm.fshr.i8(i8, i8, i8)
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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; General case - all operands can be variables.
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define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: fshl_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w9, w2, #0x1f
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; CHECK-NEXT: neg w9, w9
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; CHECK-NEXT: lsl w8, w0, w2
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; CHECK-NEXT: lsr w9, w1, w9
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: tst w2, #0x1f
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; CHECK-NEXT: csel w0, w0, w8, eq
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
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ret i32 %f
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}
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; Verify that weird types are minimally supported.
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declare i37 @llvm.fshl.i37(i37, i37, i37)
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define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
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; CHECK-LABEL: fshl_i37:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x10, #31883
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; CHECK-NEXT: movk x10, #3542, lsl #16
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; CHECK-NEXT: movk x10, #51366, lsl #32
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; CHECK-NEXT: and x9, x2, #0x1fffffffff
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; CHECK-NEXT: movk x10, #56679, lsl #48
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; CHECK-NEXT: umulh x10, x9, x10
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; CHECK-NEXT: mov w11, #37
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; CHECK-NEXT: lsr x10, x10, #5
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; CHECK-NEXT: msub x9, x10, x11, x9
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; CHECK-NEXT: and x8, x1, #0x1fffffffff
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; CHECK-NEXT: sub x11, x11, x9
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; CHECK-NEXT: lsl x10, x0, x9
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; CHECK-NEXT: lsr x8, x8, x11
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; CHECK-NEXT: orr x8, x10, x8
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; CHECK-NEXT: cmp x9, #0 // =0
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; CHECK-NEXT: csel x0, x0, x8, eq
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; CHECK-NEXT: ret
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%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
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ret i37 %f
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}
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; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
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declare i7 @llvm.fshl.i7(i7, i7, i7)
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define i7 @fshl_i7_const_fold() {
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; CHECK-LABEL: fshl_i7_const_fold:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, #67
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; CHECK-NEXT: ret
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%f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
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ret i7 %f
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}
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define i8 @fshl_i8_const_fold_overshift_1() {
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; CHECK-LABEL: fshl_i8_const_fold_overshift_1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, wzr, #0x80
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
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ret i8 %f
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}
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define i8 @fshl_i8_const_fold_overshift_2() {
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; CHECK-LABEL: fshl_i8_const_fold_overshift_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, wzr, #0x78
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshl.i8(i8 15, i8 15, i8 11)
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ret i8 %f
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}
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define i8 @fshl_i8_const_fold_overshift_3() {
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; CHECK-LABEL: fshl_i8_const_fold_overshift_3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshl.i8(i8 0, i8 225, i8 8)
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ret i8 %f
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}
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; With constant shift amount, this is 'extr'.
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define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_i32_const_shift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: extr w0, w0, w1, #23
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
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ret i32 %f
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}
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; Check modulo math on shift amount.
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define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_i32_const_overshift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: extr w0, w0, w1, #23
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
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ret i32 %f
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}
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; 64-bit should also work.
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define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
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; CHECK-LABEL: fshl_i64_const_overshift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: extr x0, x0, x1, #23
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; CHECK-NEXT: ret
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
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ret i64 %f
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}
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; This should work without any node-specific logic.
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define i8 @fshl_i8_const_fold() {
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; CHECK-LABEL: fshl_i8_const_fold:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, wzr, #0x80
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
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ret i8 %f
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}
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; Repeat everything for funnel shift right.
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; General case - all operands can be variables.
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define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: fshr_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w9, w2, #0x1f
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; CHECK-NEXT: neg w9, w9
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; CHECK-NEXT: lsr w8, w1, w2
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; CHECK-NEXT: lsl w9, w0, w9
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; CHECK-NEXT: orr w8, w9, w8
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; CHECK-NEXT: tst w2, #0x1f
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; CHECK-NEXT: csel w0, w1, w8, eq
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
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ret i32 %f
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}
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; Verify that weird types are minimally supported.
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declare i37 @llvm.fshr.i37(i37, i37, i37)
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define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
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; CHECK-LABEL: fshr_i37:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x10, #31883
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; CHECK-NEXT: movk x10, #3542, lsl #16
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; CHECK-NEXT: movk x10, #51366, lsl #32
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; CHECK-NEXT: and x9, x2, #0x1fffffffff
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; CHECK-NEXT: movk x10, #56679, lsl #48
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; CHECK-NEXT: umulh x10, x9, x10
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; CHECK-NEXT: mov w11, #37
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; CHECK-NEXT: lsr x10, x10, #5
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; CHECK-NEXT: msub x9, x10, x11, x9
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; CHECK-NEXT: and x8, x1, #0x1fffffffff
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; CHECK-NEXT: sub x10, x11, x9
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; CHECK-NEXT: lsr x8, x8, x9
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; CHECK-NEXT: lsl x10, x0, x10
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; CHECK-NEXT: orr x8, x10, x8
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; CHECK-NEXT: cmp x9, #0 // =0
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; CHECK-NEXT: csel x0, x1, x8, eq
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; CHECK-NEXT: ret
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%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
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ret i37 %f
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}
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; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
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declare i7 @llvm.fshr.i7(i7, i7, i7)
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define i7 @fshr_i7_const_fold() {
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; CHECK-LABEL: fshr_i7_const_fold:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, wzr, #0x1f
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; CHECK-NEXT: ret
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%f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
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ret i7 %f
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}
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define i8 @fshr_i8_const_fold_overshift_1() {
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; CHECK-LABEL: fshr_i8_const_fold_overshift_1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, wzr, #0xfe
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
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ret i8 %f
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}
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define i8 @fshr_i8_const_fold_overshift_2() {
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; CHECK-LABEL: fshr_i8_const_fold_overshift_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, #225
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)
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ret i8 %f
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}
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define i8 @fshr_i8_const_fold_overshift_3() {
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; CHECK-LABEL: fshr_i8_const_fold_overshift_3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, wzr, #0xff
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
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ret i8 %f
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}
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; With constant shift amount, this is 'extr'.
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define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
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; CHECK-LABEL: fshr_i32_const_shift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: extr w0, w0, w1, #9
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
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ret i32 %f
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}
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; Check modulo math on shift amount. 41-32=9.
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define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
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; CHECK-LABEL: fshr_i32_const_overshift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: extr w0, w0, w1, #9
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
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ret i32 %f
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}
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; 64-bit should also work. 105-64 = 41.
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define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
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; CHECK-LABEL: fshr_i64_const_overshift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: extr x0, x0, x1, #41
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; CHECK-NEXT: ret
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
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ret i64 %f
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}
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; This should work without any node-specific logic.
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define i8 @fshr_i8_const_fold() {
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; CHECK-LABEL: fshr_i8_const_fold:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, wzr, #0xfe
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
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ret i8 %f
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}
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define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_i32_shift_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 32)
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ret i32 %f
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}
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define i32 @fshr_i32_shift_by_bitwidth(i32 %x, i32 %y) {
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; CHECK-LABEL: fshr_i32_shift_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, w1
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 32)
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ret i32 %f
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}
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define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: fshl_v4i32_shift_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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define <4 x i32> @fshr_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: fshr_v4i32_shift_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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