llvm-mirror/test/CodeGen/AArch64/i1-contents.ll
David Blaikie ab043ff680 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00

56 lines
1.5 KiB
LLVM

; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
%big = type i32
@var = global %big 0
; AAPCS: low 8 bits of %in (== w0) will be either 0 or 1. Need to extend to
; 32-bits.
define void @consume_i1_arg(i1 %in) {
; CHECK-LABEL: consume_i1_arg:
; CHECK: and [[BOOL32:w[0-9]+]], w0, #{{0x1|0xff}}
; CHECK: str [[BOOL32]], [{{x[0-9]+}}, :lo12:var]
%val = zext i1 %in to %big
store %big %val, %big* @var
ret void
}
; AAPCS: low 8 bits of %val1 (== w0) will be either 0 or 1. Need to extend to
; 32-bits (doesn't really matter if it's from 1 or 8 bits).
define void @consume_i1_ret() {
; CHECK-LABEL: consume_i1_ret:
; CHECK: bl produce_i1_ret
; CHECK: and [[BOOL32:w[0-9]+]], w0, #{{0x1|0xff}}
; CHECK: str [[BOOL32]], [{{x[0-9]+}}, :lo12:var]
%val1 = call i1 @produce_i1_ret()
%val = zext i1 %val1 to %big
store %big %val, %big* @var
ret void
}
; AAPCS: low 8 bits of w0 must be either 0 or 1. Need to mask them off.
define i1 @produce_i1_ret() {
; CHECK-LABEL: produce_i1_ret:
; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
; CHECK: and w0, [[VAR32]], #{{0x1|0xff}}
%val = load %big, %big* @var
%val1 = trunc %big %val to i1
ret i1 %val1
}
define void @produce_i1_arg() {
; CHECK-LABEL: produce_i1_arg:
; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
; CHECK: and w0, [[VAR32]], #{{0x1|0xff}}
; CHECK: bl consume_i1_arg
%val = load %big, %big* @var
%val1 = trunc %big %val to i1
call void @consume_i1_arg(i1 %val1)
ret void
}
;define zeroext i1 @foo(i8 %in) {
; %val = trunc i8 %in to i1
; ret i1 %val
;}