llvm-mirror/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

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# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s
--- |
define i1 @no-clobber-zr(i64* %p, i64 %x) { ret i1 0 }
...
---
# Check that write of xzr doesn't inhibit pairing of xzr stores since
# it isn't actually clobbered. Written as a MIR test to avoid
# schedulers reordering instructions such that SUBS doesn't appear
# between stores.
# CHECK-LABEL: name: no-clobber-zr
# CHECK: STPXi $xzr, $xzr, $x0, 0
name: no-clobber-zr
body: |
bb.0:
liveins: $x0, $x1
STRXui $xzr, $x0, 0 :: (store 8 into %ir.p)
dead $xzr = SUBSXri killed $x1, 0, 0, implicit-def $nzcv
$w8 = CSINCWr $wzr, $wzr, 1, implicit killed $nzcv
STRXui $xzr, killed $x0, 1 :: (store 8 into %ir.p)
$w0 = ORRWrs $wzr, killed $w8, 0
RET $lr, implicit $w0
...