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When branch target identification is enabled, we can only do indirect tail-calls through x16 or x17. This means that the outliner can't transform a BLR instruction at the end of an outlined region into a BR. Differential revision: https://reviews.llvm.org/D52869 llvm-svn: 343969
45 lines
1.7 KiB
YAML
45 lines
1.7 KiB
YAML
# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
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# AArch64 Branch Target Enforcement treats the BR and BLR indirect branch
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# instructions differently. The BLR instruction can only target a BTI C
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# instruction, and the BR instruction can only target a BTI J instruction. We
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# always start indirectly-called functions with BTI C, so the outliner must not
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# transform a BLR instruction into a BR instruction.
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# There is an exception to this: BR X16 and BR X17 can also target a BTI C
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# instruction. We make of this for general tail-calls (tested elsewhere), but
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# don't currently make use of this in the outliner.
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# CHECK-NOT: OUTLINED_FUNCTION_
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--- |
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@g = hidden local_unnamed_addr global i32 0, align 4
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define hidden void @bar(void ()* nocapture %f) "branch-target-enforcement" {
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entry:
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ret void
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}
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declare void @foo()
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...
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---
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name: bar
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x20, $x21, $lr, $x19
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HINT 34
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STRWui renamable $w21, renamable $x20, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g)
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BLR renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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STRWui renamable $w21, renamable $x20, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g)
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BLR renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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STRWui killed renamable $w21, killed renamable $x20, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g)
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BLR killed renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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TCRETURNdi @foo, 0, csr_aarch64_aapcs, implicit $sp
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...
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