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5f32a8dbc4
Currently a vector move of 0 or -1 will use different instructions depending on the size of the vector. Using a single instruction (the 128-bit one) for both gives more opportunity for Machine CSE to eliminate instructions. Differential Revision: https://reviews.llvm.org/D53579 llvm-svn: 345270
74 lines
2.0 KiB
LLVM
74 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-linux-gnuabi -O2 -tail-dup-placement=0 | FileCheck %s
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; -tail-dup-placement causes tail duplication during layout. This breaks the
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; assumptions of the test case as written (specifically, it creates an
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; additional cmp instruction, creating a false positive), so we pass
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; -tail-dup-placement=0 to restore the original behavior
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; marked as external to prevent possible optimizations
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@a = external global i32
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@b = external global i32
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@c = external global i32
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@d = external global i32
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@e = external global i32
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define void @combine-sign-comparisons-by-cse(i32 *%arg) {
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; CHECK: cmp
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; CHECK: b.ge
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; CHECK-NOT: cmp
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; CHECK: b.le
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entry:
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%a = load i32, i32* @a, align 4
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%b = load i32, i32* @b, align 4
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%c = load i32, i32* @c, align 4
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%d = load i32, i32* @d, align 4
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%e = load i32, i32* @e, align 4
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%cmp = icmp slt i32 %a, %e
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br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
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land.lhs.true:
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%cmp1 = icmp eq i32 %b, %c
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br i1 %cmp1, label %return, label %if.end
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lor.lhs.false:
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%cmp2 = icmp sgt i32 %a, %e
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br i1 %cmp2, label %land.lhs.true3, label %if.end
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land.lhs.true3:
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%cmp4 = icmp eq i32 %b, %d
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br i1 %cmp4, label %return, label %if.end
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if.end:
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br label %return
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return:
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%retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]
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store i32 %a, i32 *%arg
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ret void
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}
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define void @combine_vector_zeros(<8 x i8>* %p, <16 x i8>* %q) {
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; CHECK-LABEL: combine_vector_zeros:
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; CHECK: movi v[[REG:[0-9]+]].2d, #0
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; CHECK-NOT: movi
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; CHECK: str d[[REG]], [x0]
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; CHECK: str q[[REG]], [x1]
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entry:
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store <8 x i8> zeroinitializer, <8 x i8>* %p
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store <16 x i8> zeroinitializer, <16 x i8>* %q
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ret void
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}
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define void @combine_vector_ones(<2 x i32>* %p, <4 x i32>* %q) {
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; CHECK-LABEL: combine_vector_ones:
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; CHECK: movi v[[REG:[0-9]+]].2d, #0xffffffffffffffff
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; CHECK-NOT: movi
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; CHECK: str d[[REG]], [x0]
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; CHECK: str q[[REG]], [x1]
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entry:
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store <2 x i32> <i32 -1, i32 -1>, <2 x i32>* %p
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store <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32>* %q
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ret void
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}
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