llvm-mirror/test/CodeGen/AArch64/movimm-wzr.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

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# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
--- |
; ModuleID = 'simple.ll'
source_filename = "simple.ll"
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-gnu"
define i32 @test_mov_0() {
ret i32 42
}
...
---
name: test_mov_0
alignment: 2
exposesReturnsTwice: false
tracksRegLiveness: false
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0 (%ir-block.0):
$wzr = MOVi32imm 42
$xzr = MOVi64imm 42
RET_ReallyLR implicit killed $w0
...
# CHECK: bb.0
# CHECK-NEXT: RET undef $lr