llvm-mirror/test/CodeGen/AArch64/mul-lohi.ll
Sebastian Pop 828720bb36 instr-combiner: sum up all latencies of the transformed instructions
We have found that -- when the selected subarchitecture has a scheduling model
and we are not optimizing for size -- the machine-instruction combiner uses a
too-simple algorithm to compute the cost of one of the two alternatives [before
and after running a combining pass on a section of code], and therefor it throws
away the combination results too often.

This fix has the potential to help any ISA with the potential to combine
instructions and for which at least one subarchitecture has a scheduling model.
As of now, this is only known to definitely affect AArch64 subarchitectures with
a scheduling model.

Regression tested on AMD64/GNU-Linux, new test case tested to fail on an
unpatched compiler and pass on a patched compiler.

Patch by Abe Skolnik and Sebastian Pop.

llvm-svn: 289399
2016-12-11 19:39:32 +00:00

50 lines
1.5 KiB
LLVM

; RUN: llc -mtriple=arm64-apple-ios7.0 -mcpu=cyclone %s -o - | FileCheck %s
; RUN: llc -mtriple=aarch64_be-linux-gnu -mcpu=cyclone %s -o - | FileCheck --check-prefix=CHECK-BE %s
define i128 @test_128bitmul(i128 %lhs, i128 %rhs) {
; CHECK-LABEL: test_128bitmul:
; CHECK: umulh [[HI:x[0-9]+]], x0, x2
; CHECK: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
; CHECK-DAG: mul x0, x0, x2
; CHECK-NEXT: ret
; CHECK-BE-LABEL: test_128bitmul:
; CHECK-BE: umulh [[HI:x[0-9]+]], x1, x3
; CHECK-BE: madd [[TEMP1:x[0-9]+]], x1, x2, [[HI]]
; CHECK-BE-DAG: madd x0, x0, x3, [[TEMP1]]
; CHECK-BE-DAG: mul x1, x1, x3
; CHECK-BE-NEXT: ret
%prod = mul i128 %lhs, %rhs
ret i128 %prod
}
; The machine combiner should create madd instructions when
; optimizing for size because that's smaller than mul + add.
define i128 @test_128bitmul_optsize(i128 %lhs, i128 %rhs) optsize {
; CHECK-LABEL: test_128bitmul_optsize:
; CHECK: umulh [[HI:x[0-9]+]], x0, x2
; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
; CHECK-DAG: mul x0, x0, x2
; CHECK-NEXT: ret
%prod = mul i128 %lhs, %rhs
ret i128 %prod
}
define i128 @test_128bitmul_minsize(i128 %lhs, i128 %rhs) minsize {
; CHECK-LABEL: test_128bitmul_minsize:
; CHECK: umulh [[HI:x[0-9]+]], x0, x2
; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
; CHECK-DAG: mul x0, x0, x2
; CHECK-NEXT: ret
%prod = mul i128 %lhs, %rhs
ret i128 %prod
}