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https://github.com/RPCS3/llvm-mirror.git
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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
89 lines
2.7 KiB
LLVM
89 lines
2.7 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
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;CHECK: mla {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%tmp1 = mul <8 x i8> %A, %B;
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%tmp2 = add <8 x i8> %C, %tmp1;
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ret <8 x i8> %tmp2
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}
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define <16 x i8> @mla16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
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;CHECK: mla {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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%tmp1 = mul <16 x i8> %A, %B;
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%tmp2 = add <16 x i8> %C, %tmp1;
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ret <16 x i8> %tmp2
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}
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define <4 x i16> @mla4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
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;CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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%tmp1 = mul <4 x i16> %A, %B;
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%tmp2 = add <4 x i16> %C, %tmp1;
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ret <4 x i16> %tmp2
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}
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define <8 x i16> @mla8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
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;CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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%tmp1 = mul <8 x i16> %A, %B;
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%tmp2 = add <8 x i16> %C, %tmp1;
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ret <8 x i16> %tmp2
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}
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define <2 x i32> @mla2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
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;CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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%tmp1 = mul <2 x i32> %A, %B;
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%tmp2 = add <2 x i32> %C, %tmp1;
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @mla4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
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;CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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%tmp1 = mul <4 x i32> %A, %B;
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%tmp2 = add <4 x i32> %C, %tmp1;
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ret <4 x i32> %tmp2
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}
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define <8 x i8> @mls8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
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;CHECK: mls {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%tmp1 = mul <8 x i8> %A, %B;
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%tmp2 = sub <8 x i8> %C, %tmp1;
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ret <8 x i8> %tmp2
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}
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define <16 x i8> @mls16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
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;CHECK: mls {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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%tmp1 = mul <16 x i8> %A, %B;
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%tmp2 = sub <16 x i8> %C, %tmp1;
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ret <16 x i8> %tmp2
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}
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define <4 x i16> @mls4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
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;CHECK: mls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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%tmp1 = mul <4 x i16> %A, %B;
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%tmp2 = sub <4 x i16> %C, %tmp1;
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ret <4 x i16> %tmp2
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}
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define <8 x i16> @mls8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
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;CHECK: mls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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%tmp1 = mul <8 x i16> %A, %B;
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%tmp2 = sub <8 x i16> %C, %tmp1;
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ret <8 x i16> %tmp2
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}
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define <2 x i32> @mls2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
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;CHECK: mls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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%tmp1 = mul <2 x i32> %A, %B;
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%tmp2 = sub <2 x i32> %C, %tmp1;
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @mls4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
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;CHECK: mls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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%tmp1 = mul <4 x i32> %A, %B;
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%tmp2 = sub <4 x i32> %C, %tmp1;
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ret <4 x i32> %tmp2
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}
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