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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
30 lines
956 B
YAML
30 lines
956 B
YAML
# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=machine-scheduler 2>&1 | FileCheck %s
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# REQUIRES: asserts
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--- |
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define void @func() { ret void }
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...
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---
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# Check that the instructions are not dependent on each other, even though
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# they all read/write to the zero register.
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# CHECK-LABEL: MI Scheduling
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# CHECK: SU(0): dead $wzr = SUBSWri $w1, 0, 0, implicit-def dead $nzcv
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# CHECK: # succs left : 0
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# CHECK-NOT: Successors:
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# CHECK: SU(1): $w2 = COPY $wzr
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# CHECK: # succs left : 0
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# CHECK-NOT: Successors:
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# CHECK: SU(2): dead $wzr = SUBSWri $w3, 0, 0, implicit-def dead $nzcv
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# CHECK: # succs left : 0
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# CHECK-NOT: Successors:
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# CHECK: SU(3): $w4 = COPY $wzr
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# CHECK: # succs left : 0
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# CHECK-NOT: Successors:
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name: func
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body: |
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bb.0:
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dead $wzr = SUBSWri $w1, 0, 0, implicit-def dead $nzcv
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$w2 = COPY $wzr
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dead $wzr = SUBSWri $w3, 0, 0, implicit-def dead $nzcv
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$w4 = COPY $wzr
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...
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